FPGA applications are demanding higher memory bandwidth and greater performance. To meet these requirements, we offer external memory solutions that are faster, better, and easier to use.

In this 15-minute webcast, you’ll learn:

• How we achieved 1066-MHz DDR3 interfaces in our 28-nm Stratix® V FPGAs.
• How we enhanced our memory intellectual property (IP) through extensive verification and more accurate timing models.
• Read More → "Achieving 1066-MHz DDR3 Performance With Advanced Silicon and Memory IP"

Xilinx® FPGAs offer up to 2 million logic cells incapacity—and they continue to grow. Designs of thiscomplexity usually require a team of developers, and often, a team leader, who is responsible for the synthesis and implementation of the entire design.To  make  matters  more  challenging,  the  developers can be located internationally, with different portions of the design developed in different locations, and even by different companies. The Xilinx Team Design flow introduced in ISE® DesignSuite 13.1 focuses on solving these challenges.

Increasingly, FPGA designs are no longer just the“glue logic” of the past; they are becoming morecomplex every year, often incorporating challengingIP such as PCI Express® cores. The complex modules in newer designs, even when not changing, can present difficulties when attempting to meet quality of-result (QoR) requirements. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well.

The design preservation flow solves this issue by allowing the customer to meet timing on … Read More → "Repeatable Results with Design Preservation"