Increasingly, FPGA designs are no longer just the“glue logic” of the past; they are becoming morecomplex every year, often incorporating challengingIP such as PCI Express® cores. The complex modules in newer designs, even when not changing, can present difficulties when attempting to meet quality of-result (QoR) requirements. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well.

The design preservation flow solves this issue by allowing the customer to meet timing on the critical module(s) of the design and then reuse the implementation results in future iterations. Thisreduces the number of implementation iterations in the timing closure phase of the design.