Articles – Page 236

Methods and Tools for Bring-Up and Debug of an FPGA-Based ASIC Prototype

May 17, 2012

Software simulation of RTL is no longer capable of providing all of the verification required for today’s complex ASIC designs. Modern ASICs are a complex mixture of hardware and software, so it is necessary to verify the design within the context of the complete system, running the full range of software at speeds that approach real-time. Successfully validating an ASIC design on an FPGA-based prototype before committing to silicon is now a key project milestone for most design teams. This paper examines some of the best practices for both successful bring-up … Read More → "Methods and Tools for Bring-Up and Debug of an FPGA-Based ASIC Prototype"

Bondage & Discipline

Begging for More Accuracy from your Timing Chain?

by Jim Turley

May 17, 2012

We’re all slaves to time; some more than others. Come, slave, it’s time to submit to a new form of discipline.

Hardcore readers will recall fondly our November article on Symmetricom, the company that whips time into shape, beating it into submission for the satisfaction of embedded designers everywhere. The House of Intervallic Domination now has a new offering: a GPS Disciplined Oscillator (GPSDO) that is more, shall we say, obedient than standard oscillators.

What’s a disciplined oscillator? … Read More → "Bondage & Discipline"

Racing Electronics

by Dick Selwood

May 16, 2012

One of the perks of writing about electronics is that you get to see some really cool stuff. And while motor racing is not at the top of my list of enthusiasms, an invitation by Freescale to visit the McLaren Technology Centre was just too good to pass up. Besides which, it turned my fellow hacks on EE Journal green with envy: there are some real petrol heads, including a race driver and a Formula 1 Fanatic.

The reason for the invitation is that Freescale’s processors are the intelligence in the engine control units (ECU) that McLaren … Read More → "Racing Electronics"

MIPS Plants a New Family Tree

“Aptiv” Line of Processors: the Start of a New Generation

by Jim Turley

May 14, 2012

Blame BMW. Or maybe Sears, Roebuck & Co. The trend of classifying all your products into clearly defined low, middle, and high ranges has now extended its grasp to MIPS Technologies.

Carmakers figured out a long time ago that it would help sell cars if consumers could keep all the confusing model numbers straight. Thus, General Motors had its Chevrolet brand (low end), its Buicks (midrange), and its Cadillacs (high end). That branding strategy served the company quite well, even when all three cars were actually the same vehicle with different hood ornaments.

Same goes … Read More → "MIPS Plants a New Family Tree"

The Process of Process Tracking

Satin Attempts to Corral a Recalcitrant Beast

by Bryon Moyer

May 14, 2012

Want to scare an engineer? There’s an easy weapon out there. And it consists of only one word.

“Process.”

Process is supposed to mean that a company has a formula, that they have a way of doing things that works, and that it’s repeatable, and – most importantly – that it’s a feature of the company, not some individual that works there. That means the process survives even when key people are no longer working there.

Looked at in this light, process brings order to chaos, keeps old problems from … Read More → "The Process of Process Tracking"

An EDA Foil Hat

iROC Attacks Cosmic Attacks

by Bryon Moyer

May 10, 2012

We are all under attack. Don’t bother hiding the kids; there is no escape. Well, not much, anyway. A foil hat won’t be enough to protect them, and they’d be totally abused at school in a full-body foil outfit.

This constant bombardment isn’t news; it’s the familiar neutron (amongst other particles) assault that comes from space or the materials around us. And it’s just waiting to mess up the system you designed.

There’s a proliferation of “Df’s,” and, joining DfT and DfM (referring to design for test … Read More → "An EDA Foil Hat"

I, Robot 101

School Uses Robotics to Teach Engineering and More

by Jim Turley

May 9, 2012

Okay, it’s now officially the Twenty-First Century: They’re teaching robotics in school.

I, for one, welcome our robot overlords, especially if they’re like the ones coming out of a small Arizona high school. Last week, I had a nice talk with Enrique Santa Cruz, the Robotics & Automation instructor at Walden Grove High School in Sahuarita, Arizona. (I’ll save you the trouble: it’s a town of 25,000 souls about 15 miles due south of Tucson. You’re welcome.)

Walden High has a robot-building competition every year, and the competition is tough. Teams … Read More → "I, Robot 101"

Power When You Need It

Aldec Harnesses Massive Server Capacity

by Kevin Morris

May 8, 2012

Warning! We are going to say the “C” word in this article. If you can’t take it, just stop reading now and save yourself a lot of heartache and grief. We know a lot of you are sensitive on this topic and have deep-rooted emotional issues about it. Our advice is to seek professional counseling.

For those of you who are less delicate (we assume you’re still reading), we proudly present a system that has the potential to accelerate your design verification efforts beyond anything you could currently achieve. You know how it goes. You … Read More → "Power When You Need It"

True 3D MEMS

Work at MIT Takes MEMS beyond Quasi-3D

by Bryon Moyer

May 7, 2012

Everyone is jumping on the 3D bandwagon. But if I said that MEMS was just taking some steps in that direction, you might understandably question my mental health, since, at first blush, it would seem that MEMS structures are already 3D.

After all, that most primitive MEMS element, the cantilever, to name one example, is specifically intended to move out of the wafer plane – why is that not 3D?

The movement of the cantilever may be 3D, but the structure is only quasi-3D, as explained in an MIT paper by Fabio Fachin, Brian Wardle, … Read More → "True 3D MEMS"

Verifying Today’s SoCs Requires a New Approach

by Bryon Moyer

May 3, 2012

As is well known, the system-on-chip (SoC) verification problem grows faster than design size, so it takes more time and effort to verify a complete SoC than an individual IP block. However, the problems with SoC verification are deeper than just the increase in size.

The biggest new wrinkle introduced by today’s large multicore SoC is the greater number of shared resources, sometimes called “points of convergence” by verification engineers. Every level of the bus structure is hammered by multiple master agents vying for access. Every memory is accessed by multiple processors, processing engines, and peripherals, … Read More → "Verifying Today’s SoCs Requires a New Approach"