feature article
Subscribe Now

MIPS Plants a New Family Tree

“Aptiv” Line of Processors: the Start of a New Generation

Blame BMW. Or maybe Sears, Roebuck & Co. The trend of classifying all your products into clearly defined low, middle, and high ranges has now extended its grasp to MIPS Technologies.

Carmakers figured out a long time ago that it would help sell cars if consumers could keep all the confusing model numbers straight. Thus, General Motors had its Chevrolet brand (low end), its Buicks (midrange), and its Cadillacs (high end). That branding strategy served the company quite well, even when all three cars were actually the same vehicle with different hood ornaments.

Same goes for BMW: they’ve got the 3-series, the 5-series, and the 7-series. Mercedes-Benz followed suit a few years later with its C-class, E-class, and S-class. (Never mind today’s confusing array of M-class, CLK, CL, SLK, CLS, MLK, G, GLK, SL, SLS, R-class, and more.) Even mainstream American department stores like Sears bluntly labeled their products, “Good,” “Better”, and “Best.” Not much room for confusion there.

Here in the microprocessor world, Intel adopted a similar scheme, ditching engineering-oriented part numbers like 80386 for more consumer-friendly names like Pentium, Atom, Celeron, and Core i5. (And Itanium, which proves that branding isn’t everything.) Embedded processor darling ARM has its Cortex-A, -R, and –M ranges, which serve very nicely to keep that company’s bewildering array of CPU cores straight in customers’ minds.

Now MIPS Technologies has borrowed a chapter from GM’s playbook by branding its new processors “Aptiv” and subdividing the new brand into three subcategories. Starting to see the pattern here? Henceforth the low-end MIPS processors will be called microAptiv, the midrange CPUs will be dubbed interAptiv, and the high-end cores will be named proAptiv.

Bonus points if you noticed that the three prefixes start with the letters M, I, and P. Clever, huh? These guys are leaving nothing to chance. Any guesses when the fourth branch of S-class cores will launch?

MIPS isn’t retroactively renaming its older or existing CPU cores and squeezing them into the low/medium/high hierarchy; they all keep their confusing part numbers. Only new CPU cores get the new Aptiv branding. But over time, as MIPS gradually replaces its old cores with new ones, there will be nothing but Aptiv-class CPUs.

There’s more than just marketing hand-waving behind this announcement, though. There’s some meat to go along with the sizzle. Coincident with the rollout of the new name was the debut of three new CPU cores, one in each class. Say hello to your new Aptiv processors.

We’ll save the full-on technical analysis for a later article, but for now the new proAptiv defines the high end of the MIPS product range. It sits atop the class range with the current 74K or 1074K CPU designs, meaning it’s a 32-bit, multicore, superscalar, out-of-order machine that can dispatch as many as six instructions per clock cycle under the right conditions. In short, it’s a beast. MIPS claims that proAptiv delivers the best benchmark scores of any “soft” CPU, ever, and I don’t doubt them.

It’s pretty tough to drag race CPU cores; kind of like administering IQ tests to a brain in a jar. After all, CPU cores are just that: cores. There’s no bus interface, no memory, no peripherals or I/O, and no real workload. Cores usually do have L1 and L2 caches, but even those have to be simulated. In short, it’s dangerous to draw too many conclusions from synthetic benchmark tests run on synthesizable cores under artificial conditions.

But that won’t stop us.

MIPS quoted two different benchmarks as evidence of the superiority of its new proAptiv: Dhrystone and CoreMark. Dhrystone is a hoary old worn-out bat that has no place in 21st-century computer benchmarks – which is why it’s so popular. The oft-maligned and frequently faked Dhrystone scores show that proAptiv delivers the same performance as ARM’s high-end Cortex-A15, clock-for-clock. In other words, the DMIPS/MHz ratio for both CPU designs is the same. Given that both the numerator and the denominator in that equation are suspect, the result is doubly suspect, but at least it doesn’t favor one CPU over the other.

CoreMark, on the other hand, is considerably more useful and reliable. Developed by the nonprofit EEMBC group specifically for the purpose of benchmarking disembodied CPU cores (hence the name), CoreMark is actually a fairly accurate “finger in the breeze” estimate of the goodness of a given CPU design. And on that score, the new proAptiv is… adequate.

MIPS claims that the high-end proAptiv delivers 50% better CoreMark scores than the best published scores they could find for an ARM processor, which happens to be true. It also happens to be a Cortex-A9. They’re not comparing proAptiv to an A15; they’re comparing it to its slower cousin. It’s that “published score” thing that’s the hang-up. EEMBC doesn’t officially recognize just anyone’s CoreMark scores unless they’ve been verified and approved by EEMBC first. This prevents (they hope) wholesale fibbing about benchmark scores and helps to keep CoreMark out of the muck into which Dhrystone long ago descended. It’s a good strategy, but it also means that we don’t have a lot of published, officially sanctioned CoreMark scores to go by. This fact wasn’t lost on MIPS’s clever marketing people, who wasted no time in comparing their Cadillac to the British Buick.

Be that as it may, we can safely say that proAptiv’s performance is probably very similar to the A15’s. What proAptiv does have going for it is size: the thing is small. MIPS-based processors typically do have smaller die sizes than competing processors, even other RISC processors. That’s because the MIPS architecture is the closest thing we have to an actual, true RISC design. It really is reduced in instruction set, and that makes for a small and efficient silicon layout. In comparison, ARM, PowerPC, SPARC, and other RISC designs are comparatively complex; more like WISC (weakened instruction set computer) designs.

The new proAptiv has a lot of high-end features buried deep within its microarchitecture. As we said, we’ll save the gory details and nerd porn for a later issue. For now, it’s safe to say that it’s comparable to a Cortex-A15 in performance and capabilities, and close enough that performance will almost never be the deciding factor. So what will be?

Die size is important, but it’s getting less so all the time. People don’t put big CPU cores like proAptiv into little chips, so the relatively modest size of the CPU won’t make a big difference to the overall size of the chip it’s powering. Are a few extra mm2 of silicon worth a lot of money to you? Maybe, but most SoC designers won’t obsess over it too much.

How about proAptiv’s power consumption? No way to tell. Measuring the power usage of a CPU core is even tougher than benchmarking its performance. Yes, it has all the appropriate sleep modes and internal clock-gating features, but again, the rest of the chip will probably affect the power budget more than the CPU does.

So that leads us to cost. Is proAptiv cheaper than an A15? Almost certainly. Like AMD, MIPS must discount its prices to compete with its bigger and better-known rival. That doesn’t mean the MIPS processor in inferior in any way; it just reflects the commercial reality of competition and customer perception. MIPS Technologies has to be cheaper to even get a space at the negotiating table.

Which finally brings us to software. Most development teams have chosen their EDA framework and software-development tool chains before they choose a processor, so CPU architecture is often a foregone conclusion. If you’re an ARM shop you’re likely to remain an ARM shop no matter how wonderful the proAptiv may be. The same is true in reverse: existing MIPS users aren’t likely to jump ship to the A15. Developers using other CPU architectures are probably straddling the fence, but the majority of those straddlers have fallen into ARM’s yard, much to MIPS’s dismay. The British firm has become the de facto choice for a lot of designers. Selecting anything else may require a bit of boardroom persuasion.

So here’s to the independents – the ones who choose their hardware based on its own merits. Instead of following the herd, they evaluate, measure, test, and prototype until they’ve found the CPU that suits them best. MIPS is a good choice – its very name means performance – and the new proAptiv helps to uphold that legacy. 

3 thoughts on “MIPS Plants a New Family Tree”

  1. The FPGA companies have done this as well. First, Altera with their 3-tiered Stratix, Arria, Cyclone designations. Then, more recently, Xilinx with Kintex, Artix, Virtex. Seems like it’s a trend.

    MIPS could now come out with a series of passive components with the inAptiv designation…

  2. I think, in processor architecture diagnosis, the term is no longer “hyperAptiv” but “Application Deficit Disorder” – it’s when you have a great new processor but not many applications run on it yet…

Leave a Reply

featured blogs
Oct 15, 2021
We will not let today's gray and wet weather in Fort Worth (home of Cadence's Pointwise team) put a damper on the week's CFD news which contains something from the highbrow to the... [[ Click on the title to access the full blog on the Cadence Community site. ...
Oct 13, 2021
How many times do you search the internet each day to track down for a nugget of knowhow or tidbit of trivia? Can you imagine a future without access to knowledge?...
Oct 13, 2021
High-Bandwidth Memory (HBM) interfaces prevent bottlenecks in online games, AI applications, and more; we explore design challenges and IP solutions for HBM3. The post HBM3 Will Feed the Growing Need for Speed appeared first on From Silicon To Software....
Oct 4, 2021
The latest version of Intel® Quartus® Prime software version 21.3 has been released. It introduces many new intuitive features and improvements that make it easier to design with Intel® FPGAs, including the new Intel® Agilex'„¢ FPGAs. These new features and improvements...

featured video

DesignCon 2021 112G Ethernet & PCIe 6.0 IP Demos

Sponsored by Synopsys

This video features Synopsys' silicon-proven DesignWare 112G Ethernet and PCIe 6.0 PHY IP solutions successfully interoperating with Samtec's AI/ML edge connectors and Amphenol's Direct Attach Copper (DAC) cables with superior Bit Error Rates (BERs) at maximum performance.

Click here for more information about DesignWare 112G Ethernet PHY IP

featured paper

3 key design decisions for any desktop 3D printer design

Sponsored by Texas Instruments

Learn about three important design considerations to take your 3D print design to the next level.

Click to read more

featured chalk talk

ROHM's KX132-1211 & KX134-1211 Accelerometers

Sponsored by Mouser Electronics and ROHM Semiconductor

Machine health monitoring is a key benefit in the Industry 4.0 revolution. Integrating data from sensors for vibration detection, motion detection, angle measurement and more can give a remarkably accurate picture of machine health, and timely warning of impending failure. In this episode of Chalk Talk, Amelia Dalton chats with Alex Chernyakov of ROHM Semiconductor about the key considerations in machine health monitoring, and how a new line of accelerometers for industrial applications can help.

Click here for more information about Kionix / ROHM Semiconductor KX134 & KX132 Tri-axis Digital Accelerometers