Chip design has always consisted of a series of loops. Do something, check the effects, fix things, check again, and hopefully converge on a solution. A big part of the focus of EDA tools developers has been to make each of these passes faster and reduce the number of passes.
One of the critical things that has to be checked at the end of each layout pass is that the layout meets the design rules. A couple years ago, the DRC-checking part started … Read More → "Converging by Construction"