editor's blog
Subscribe Now

IP Block Verification

If you design SoCs, then you use IP. Lots of it, probably. From different companies, some perhaps even from your own company.

And the good news is, it’s all perfectly documented – pins, registers, timing, everything. Right? So you know that just fitting it all together will give you a correct-by-construction design. Right?

Yeah… and then you wake up.

In fact, the RTL implementation may deviate from the spec, or there may be holes in the spec, or the black-box RTL may have invisible surprises. It’s enough to make you run back to the comfort of your pillow.

Jasper and Duolog, at the urging of ARM, have come together to try to solve some of this. The first key ingredient is a machine-friendly way of describing an IP block. And that would be IP-XACT. IP-XACT doesn’t describe the IP implementation; it’s simply (if “simple” can be used here) a specification of the metadata and the interface. Like a software function or object prototype. (To be clear, Jasper and Duolog didn’t create IP-XACT; it’s been around for a while, and they simply make use of it.)

Given spec’ed and implemented versions of an IP block, Duolog and Jasper can then confirm whether specs match RTL or black-box matches white-box. That’s the first of two tools that will be available.

The second will help assemble the IP blocks into a design and then verify that everything is connected properly. “How hard can that be?” you ask. Well, given that some connections may come and go over time or given various conditions (for instance, via multiplexing), and the fact that some IP can have hundreds (or more) of connections, it can actually get pretty complicated. The tools purport to handle these scenarios, including such timing details as latency.

This all got rolled out at DAC, so it’s available today. You can find out more in their release.

Leave a Reply

featured blogs
Jan 24, 2020
Someone has created a song by taking Pi, assigning each number to a note, and adding harmonies. The result is strangely captivating....
Jan 24, 2020
[From the last episode: We looked at the different ways memory can be organized in different kinds of systems.] Let'€™s look at a scenario: you run a restaurant, but you'€™re short on funds to hire people. So you'€™re your own chief cook and bottle-washer. You do everyt...
Jan 23, 2020
Embedded design trends typically revolve around three main ideas: faster data rates, smaller form factors and cost-effective solutions. Those design trends drive the theme for the 2020 Embedded Tech Trends forum: The Business and Technology Forum for Critical and Intelligent ...
Jan 22, 2020
Master the design and verification of next gen transport: Part One – Overview Master the design and verification of next gen transport: Part Two – High-Level Synthesis Master the design and verification of next gen transport: Part Three – Functional Safety M...

Featured Video

Automotive Trends Driving New SoC Architectures -- Synopsys

Sponsored by Synopsys

Today’s automotive trends are driving new design requirements for automotive SoCs targeting ADAS, gateways, connected cars and infotainment. Find out why it is essential to use pre-designed, pre-verified, reusable automotive-optimized IP to meet such new requirements and accelerate design time.

Drive Your Next Design to Completion Today with DesignWare IP® for Automotive SoCs