editor's blog
Subscribe Now

IP Block Verification

If you design SoCs, then you use IP. Lots of it, probably. From different companies, some perhaps even from your own company.

And the good news is, it’s all perfectly documented – pins, registers, timing, everything. Right? So you know that just fitting it all together will give you a correct-by-construction design. Right?

Yeah… and then you wake up.

In fact, the RTL implementation may deviate from the spec, or there may be holes in the spec, or the black-box RTL may have invisible surprises. It’s enough to make you run back to the comfort of your pillow.

Jasper and Duolog, at the urging of ARM, have come together to try to solve some of this. The first key ingredient is a machine-friendly way of describing an IP block. And that would be IP-XACT. IP-XACT doesn’t describe the IP implementation; it’s simply (if “simple” can be used here) a specification of the metadata and the interface. Like a software function or object prototype. (To be clear, Jasper and Duolog didn’t create IP-XACT; it’s been around for a while, and they simply make use of it.)

Given spec’ed and implemented versions of an IP block, Duolog and Jasper can then confirm whether specs match RTL or black-box matches white-box. That’s the first of two tools that will be available.

The second will help assemble the IP blocks into a design and then verify that everything is connected properly. “How hard can that be?” you ask. Well, given that some connections may come and go over time or given various conditions (for instance, via multiplexing), and the fact that some IP can have hundreds (or more) of connections, it can actually get pretty complicated. The tools purport to handle these scenarios, including such timing details as latency.

This all got rolled out at DAC, so it’s available today. You can find out more in their release.

Leave a Reply

featured blogs
Jul 1, 2022
We all look for 100% perfection and want to turn our dreams (expectations) into reality as far as we can. Are you also looking for a magic wand to turn expectation into reality? The story applies to... ...
Jun 30, 2022
Learn how AI-powered cameras and neural network image processing enable everything from smartphone portraits to machine vision and automotive safety features. The post How AI Helps Cameras See More Clearly appeared first on From Silicon To Software....
Jun 28, 2022
Watching this video caused me to wander off into the weeds looking at a weird and wonderful collection of wheeled implementations....

featured video

Demo: Achronix Speedster7t 2D NoC vs. Traditional FPGA Routing

Sponsored by Achronix

This demonstration compares an FPGA design utilizing Achronix Speedster7t 2D Network on Chip (NoC) for routing signals with the FPGA device, versus using traditional FPGA routing. The 2D NoC provides a 40% reduction in logic resources required with 40% less compile time needed versus using traditional FPGA routing. Speedster7t FPGAs are optimized for high-bandwidth workloads and eliminate the performance bottlenecks associated with traditional FPGAs.

Subscribe to Achronix's YouTube channel for the latest videos on how to accelerate your data using FPGAs and eFPGA IP

featured paper

Addressing high-voltage design challenges with reliable and affordable isolation tech

Sponsored by Texas Instruments

Check out TI’s new white paper for an overview of galvanic isolation techniques, as well as how to improve isolated designs in electric vehicles, grid infrastructure, factory automation and motor drives.

Click to read more

featured chalk talk

Faster, More Predictable Path to Multi-Chiplet Design Closure

Sponsored by Cadence Design Systems

The challenges for 3D IC design are greater than standard chip design - but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, with its 3D design planning and implementation cockpit, flow manager and co-design capabilities will not only help you with your next 3D IC design.

Click here for more information about Integrity 3D-IC Platform from Cadence Design Systems