editor's blog
Subscribe Now

Converging by Construction

Chip design has always consisted of a series of loops. Do something, check the effects, fix things, check again, and hopefully converge on a solution. A big part of the focus of EDA tools developers has been to make each of these passes faster and reduce the number of passes.

One of the critical things that has to be checked at the end of each layout pass is that the layout meets the design rules. A couple years ago, the DRC-checking part started moving to real-time with Mentor’s Calibre tool, which dominates DRC checking. It started with Mentor’s own InRoute (for digital) and then RealTime, for integration into custom layout tools like Laker (was Springsoft, now Synopsys). This meant that DRC rules were checked immediately with each layout change, eliminating one aspect of the long loop.

Not comprehended in that, however, was the electrical aspects of layout – the Rs and Cs (mostly parasitic) that accrue as you lay your chip out. Cadence has just announced a change to that. They call it “electrically-aware design,” and it moves the extraction and parts of verification from the end of the loop to “real-time.” You can feed forward voltage/current points from circuit simulation and monitor as you do layout; you can establish constraints and track adherence; you can get warnings when something you’ve done in layout creates an electromagnetic issue. You push a polygon and the tools recalculate the parasitics and update the performance numbers immediately, alerting if necessary.

The big win here is that it allows designers to “converge by construction” instead of doing an entire layout and then finding all the issues. It also lets designers push the edge a bit more. If you’re tight on your schedule (who isn’t?), then you might over-design to get things to pass – you’re not then going to go back and “back things off” until they fail in order to optimize since that will take too long. But with the real-time view of the impact of layout, you can see if you’ve over-designed and then make immediate adjustments to achieve a better balance.

It’s a simple concept with interesting potential for custom and analog designers. (And if you’re wondering about real-time DRC, Cadence already has that in place as well.)

You can find more details in their release.

Leave a Reply

featured blogs
Dec 2, 2022
A picture tells more than a thousand words, so here are some pictures of CadenceLIVE Europe 2023 Academic and Entrepreneur Tracks to tell a story. After two years of absence, finally the Academic Dinner could take place with professors from Lead Institutions and Program Chair...
Nov 30, 2022
By Chris Clark, Senior Manager, Synopsys Automotive Group The post How Software-Defined Vehicles Expand the Automotive Revenue Stream appeared first on From Silicon To Software....
Nov 30, 2022
By Joe Davis Sponsored by France's ElectroniqueS magazine, the Electrons d'Or Award program identifies the most innovative products of the… ...
Nov 18, 2022
This bodacious beauty is better equipped than my car, with 360-degree collision avoidance sensors, party lights, and a backup camera, to name but a few....

featured video

Unique AMS Emulation Technology

Sponsored by Synopsys

Learn about Synopsys' collaboration with DARPA and other partners to develop a one-of-a-kind, high-performance AMS silicon verification capability. Please watch the video interview or read it online.

Read the interview online:

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

Prognostic Health Management/Predictive Maintenance Solutions for Machines

Sponsored by Mouser Electronics and Advantech

Prognostic health management, also known as predictive maintenance, is a vital component of our industrial ecosystem. In this episode of Chalk Talk, Amelia Dalton chats with Eric Wang from Advantech about the roles that data acquisition, data processing and artificial intelligence play in prognostic health management, the challenges of building these types of systems, and what kind of predictive maintenance solution would be the best fit for your next design.

More information about Advantech WISE-750 Intelligent Vibration Gateway