editor's blog
Subscribe Now

Converging by Construction

Chip design has always consisted of a series of loops. Do something, check the effects, fix things, check again, and hopefully converge on a solution. A big part of the focus of EDA tools developers has been to make each of these passes faster and reduce the number of passes.

One of the critical things that has to be checked at the end of each layout pass is that the layout meets the design rules. A couple years ago, the DRC-checking part started moving to real-time with Mentor’s Calibre tool, which dominates DRC checking. It started with Mentor’s own InRoute (for digital) and then RealTime, for integration into custom layout tools like Laker (was Springsoft, now Synopsys). This meant that DRC rules were checked immediately with each layout change, eliminating one aspect of the long loop.

Not comprehended in that, however, was the electrical aspects of layout – the Rs and Cs (mostly parasitic) that accrue as you lay your chip out. Cadence has just announced a change to that. They call it “electrically-aware design,” and it moves the extraction and parts of verification from the end of the loop to “real-time.” You can feed forward voltage/current points from circuit simulation and monitor as you do layout; you can establish constraints and track adherence; you can get warnings when something you’ve done in layout creates an electromagnetic issue. You push a polygon and the tools recalculate the parasitics and update the performance numbers immediately, alerting if necessary.

The big win here is that it allows designers to “converge by construction” instead of doing an entire layout and then finding all the issues. It also lets designers push the edge a bit more. If you’re tight on your schedule (who isn’t?), then you might over-design to get things to pass – you’re not then going to go back and “back things off” until they fail in order to optimize since that will take too long. But with the real-time view of the impact of layout, you can see if you’ve over-designed and then make immediate adjustments to achieve a better balance.

It’s a simple concept with interesting potential for custom and analog designers. (And if you’re wondering about real-time DRC, Cadence already has that in place as well.)

You can find more details in their release.

Leave a Reply

featured blogs
Sep 21, 2023
Wireless communication in workplace wearables protects and boosts the occupational safety and productivity of industrial workers and front-line teams....
Sep 26, 2023
5G coverage from space has the potential to make connectivity to the Internet truly ubiquitous for a broad range of use cases....
Sep 26, 2023
Explore the LPDDR5X specification and learn how to leverage speed and efficiency improvements over LPDDR5 for ADAS, smartphones, AI accelerators, and beyond.The post How LPDDR5X Delivers the Speed Your Designs Need appeared first on Chip Design....
Sep 26, 2023
The eighth edition of the Women in CFD series features Mary Alarcon Herrera , a product engineer for the Cadence Computational Fluid Dynamics (CFD) team. Mary's unwavering passion and dedication toward a career in CFD has been instrumental in her success and has led her ...
Sep 21, 2023
Not knowing all the stuff I don't know didn't come easy. I've had to read a lot of books to get where I am....

Featured Video

Chiplet Architecture Accelerates Delivery of Industry-Leading Intel® FPGA Features and Capabilities

Sponsored by Intel

With each generation, packing millions of transistors onto shrinking dies gets more challenging. But we are continuing to change the game with advanced, targeted FPGAs for your needs. In this video, you’ll discover how Intel®’s chiplet-based approach to FPGAs delivers the latest capabilities faster than ever. Find out how we deliver on the promise of Moore’s law and push the boundaries with future innovations such as pathfinding options for chip-to-chip optical communication, exploring new ways to deliver better AI, and adopting UCIe standards in our next-generation FPGAs.

To learn more about chiplet architecture in Intel FPGA devices visit https://intel.ly/45B65Ij

featured paper

Intel's Chiplet Leadership Delivers Industry-Leading Capabilities at an Accelerated Pace

Sponsored by Intel

We're proud of our long history of rapid innovation in #FPGA development. With the help of Intel's Embedded Multi-Die Interconnect Bridge (EMIB), we’ve been able to advance our FPGAs at breakneck speed. In this blog, Intel’s Deepali Trehan charts the incredible history of our chiplet technology advancement from 2011 to today, and the many advantages of Intel's programmable logic devices, including the flexibility to combine a variety of IP from different process nodes and foundries, quicker time-to-market for new technologies and the ability to build higher-capacity semiconductors

To learn more about chiplet architecture in Intel FPGA devices visit: https://intel.ly/47JKL5h

featured chalk talk

Designing with GaN? Ask the Right Questions about Reliability
As demands for high-performance and low-cost power conversion increases, gallium nitride offers several intriguing benefits for next generation power supply design. In this episode of Chalk Talk, Amelia Dalton and Sandeep Bahl from Texas Instruments investigate the what, why and how of gallium nitride power technology. They take a closer look at the component level and in-system reliability for TI’s gallium nitride power solutions and why GaN might just be the perfect solution for your next power supply design.
Oct 4, 2022
40,985 views