DESIGN AUTOMATION CONFERENCE, San Francisco, Calif. – June 4, 2012 –– Chip Path Design Systems, the system-on-chip assembly company, today announced that it will be showing a new system-on-chip (SoC) and application-specific integrated circuit (ASIC) architectural assembly and floorplanning system at DAC 2012 in San Francisco, CA. A unique feature of the new tools is the ability to graphically define and integrate architecture before beginning to hunt for vendor-specific intellectual property (IP). Chip Path has developed a model catalog of common I/O channels, subsystems, and connection networks used in SoC design.

“Everyone knows the parts that vehicles are designed … Read More → "Chip Path Design Systems Announces System-on-Chip Architectural Assembly and Floorplanning System"

SAN FRANCISCO, CA–(Marketwire – June 04, 2012) – DAC Booth # 1930 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that TSMC has qualified the Cadence® Physical Verification System (PVS) for 28-nanometer design signoff, and completed Phase I certification for TSMC’s 20-nanometer process.

Designers can request a PVS 20-nanometer technology file directly … Read More → "Cadence Physical Verification System Qualified for TSMC 28nm, 20nm Process"

SAN FRANCISCO, Calif — June 4, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced today at the 49thDesign Automation Conference (DAC) the availability of a Fast Lint methodology for its SpyGlass</ … Read More → "Atrenta Introduces Fast Lint for SpyGlass®"

SAN FRANCISCO, CA–(Marketwire – June 04, 2012) – DAC Booth # 1930 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that its Encounter digital and Virtuoso custom/analog design platforms achieved TSMC Phase I certification for 20-nanometer design, implementation and verification/signoff.

TSMC certified the tools for 20-nanometer design rule manuals (DRMs) and SPICE models. Early adopters are using the flows and tools while close collaboration continues between TSMC, Cadence and designers.

The Cadence Read More → "Cadence Encounter and Virtuoso Design Platforms Receive TSMC 20nm Phase I Certification"

DESIGN AUTOMATION CONFERENCE, San Francisco, CA, June 4, 2012 –A new electronic design automation (EDA) company and a groundbreaking new product were launched at DAC 2012 today. Ausdia delivers a comprehensive timing constraints development, verification and management solution that complements all implementation and timing signoff flows. Ausdia’s Timevision, an innovative timing constraint development solution, integrates with all aspects of the design flow and is used before synthesis, before DFT insertion, before place and route, and when signoff timing is being run. Timevision helps designers create good SDC/TCL constraints and is a verification platform for existing timing constraints. The company’s … Read More → "Timing Closure Experts Launch New Company, Announce Proven Timing Constraints Platform"