industry news
Subscribe Now

Chip Path Design Systems Announces System-on-Chip Architectural Assembly and Floorplanning System

DESIGN AUTOMATION CONFERENCE, San Francisco, Calif. – June 4, 2012 –– Chip Path Design Systems, the system-on-chip assembly company, today announced that it will be showing a new system-on-chip (SoC) and application-specific integrated circuit (ASIC) architectural assembly and floorplanning system at DAC 2012 in San Francisco, CA. A unique feature of the new tools is the ability to graphically define and integrate architecture before beginning to hunt for vendor-specific intellectual property (IP). Chip Path has developed a model catalog of common I/O channels, subsystems, and connection networks used in SoC design.

“Everyone knows the parts that vehicles are designed from. There is a well-defined set of component categories,” said J. George Janac, CEO of Chip Path Design Systems. “We have built the same kind of component parts catalog for system-on-chip design, creating higher level models with a built-in connection methodology that speeds chip integration. SoCs are easier to define using these higher-level models, which in turn map onto semiconductor IP.”

The Chip Path SoC portal allows chip designers to define and integrate system-on-chip architectures using Chip Path’s SemantIC Design™ graphical interface. Architecture can be defined in a web-browser accessing a centralized knowledge database or on a local workstation. Architectures then can be mapped on foundry technology nodes for evaluation of size, power, device cost, and non-recurring engineering expenses (NRE). Chip resources or SoC architecture is defined in a web-browser. Chip Path SoC portals come in two flavors: multi-vendor portals for foundry tradeoff analysis and branded portals for the world’s leading integrated circuit (IC) foundries and IP vendors. Each portal contains three basic tools. First is the system-on-chip architectural tool that maps to various SoC architectures. Existing nodes include 28nm to 0.35um; extrapolated planning nodes include 14nm to 22nm. Second is the IP Directory that allows users to search for various IP types from over 14,000 entries. The third tool enables simple form entry of high level resources like I/O, SERDES transceivers, memories, gates, clocks, etc., with simultaneous mapping onto multiple nodes for sizing and cost estimation. Chip Path’s goal is to make system-on-chip design possible at half the cost by removing risk and allowing projects to start earlier with full implementation knowledge.

The ChipPlanner™ front-end floorplanning tools provide the link between the web-based architectural tools and semiconductor IP selection and evaluation. These tools feature block and network-on-chip (NOC)-based floorplanning backup by RTL estimation. (Physical RTL is a Verilog estimation tool for IP evaluation that features RTL estimation, placement, timing evaluation, and congestion analysis.) ChipPlanner’s back end tools link to the synthesis place and route (SPR) flows in use today. Both versions of ChipPlanner run on Linux and are web connected to information servers.

How does the semiconductor IP supply chain integrate with Chip Path? Each SemantIC model maps in turn to IP vendor parts for implementation. Often, a channel like USB will need a Synopsys PHY, a HighIP USB controller, TrueCircuits PLL and use an ARM memory buffer and TSMC standard cells. Designers simply do not want to be burdened with these details in the architecture phase. Key to the Chip Path tools is the ability to link models to vendors and even to external chips. Perhaps the USB controller exports a digital ULPI+ interface from the SoC and needs to link to a TI or SMSC external PHY chip. These links enable selection of vendors based on final implementation choice.

Chip Path is previewing some of its tools on its website. Registered users can come to: Various tools and portals can be accessed from its root. Downloadable tools are available by contacting sales. In addition, tools will be on display at the Design Automation Conference (DAC) from June 4-7 in San Francisco, CA in Booth #306.

About Chip Path

Chip Path Design Systems is a privately funded company dedicated to system-on-chip (SoC) architectural assembly that merges design, electronic design automation, and semiconductor IP. Targeting the front-end process from specification through IP assembly to physical planning, Chip Path delivers tools based on semiconductor IP for creation of new designs/devices as well as using existing devices that span SoC, FPGA, FPASSP, and ASSP.

The company is headquartered in Cupertino, Calif. 95014. Telephone: 408-257-3643. Email: Website:

Leave a Reply

featured blogs
Jan 26, 2021
I could doubtless extend this series all year long, covering the important updates, improvements, and completely new functionality that is continually being added to the Allegro ® Package... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Jan 25, 2021
In which we meet the Photomath calculator, which works with photos of your equations, and the MyScript calculator, which allows you to draw equations with your finger....
Jan 25, 2021
A mechanical look at connector skew in your systems.  Electrical and Mechanical requirements collide when looking at interconnects in your electrical system. What can you do about it, how do you plan for it, and how do you pick the most rugged solution that still carries...
Jan 20, 2021
Explore how EDA tools & proven IP accelerate the automotive design process and ensure compliance with Automotive Safety Integrity Levels & ISO requirements. The post How EDA Tools and IP Support Automotive Functional Safety Compliance appeared first on From Silicon...

featured paper

Speeding Up Large-Scale EM Simulation of ICs Without Compromising Accuracy

Sponsored by Cadence Design Systems

With growing on-chip RF content, electromagnetic (EM) simulation of passives is critical — from selecting the right RF design candidates to detecting parasitic coupling. Being on-chip, accurate EM analysis requires a tie in to the process technology with process design kits (PDKs) and foundry-certified EM simulation technology. Anything short of that could compromise the RFIC’s functionality. Learn how to get the highest-in-class accuracy and 10X faster analysis.

Click here to download the whitepaper

featured chalk talk

Fundamentals of ESD/TVS Protection

Sponsored by Mouser Electronics and Nexperia

ESD protection is a critical, and often overlooked design consideration in many of today’s systems. There is a wide variety of solutions available for ESD protection, and choosing the right one for your design can be a daunting and confusing task. In this episode of Chalk Talk, Amelia Dalton chats with Tom Wolf of Nexperia about choosing the right ESD protection for your next design.

Click here for more information about Nexperia PCMFxUSB3B/C - CMF EMI filters with ESD Protection