industry news
Subscribe Now

Atrenta Introduces Fast Lint for SpyGlass®

SAN FRANCISCO, Calif — June 4, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industriesannounced today at the 49thDesign Automation Conference (DAC) the availability of a Fast Lint methodology for its SpyGlass RTL analysis and optimization platform.  The new capability is part of Atrenta’s GuideWarereference methodology, and tests on a wide range of designs have shown a 4X to 9X speed improvement while still delivering accurate, low noise results.

In addition to Fast Lint, the company will be demonstrating hierarchical analysis support, which abstracts design elements that have been pre-analyzed for higher (chip-level) analysis.  This approach can deliver 5X to over an order-of-magnitude speed improvement for highly complex designs as compared to running flat (i.e., without hierarchy).

The SpyGlass linting solution analyzes a design at the register transfer level (RTL) of abstraction for coding styles and circuit constructs that can cause verification and implementation issues. Linting forms the base capability for the SpyGlass platform, which is also used widely for power optimization, clock synchronization verification (CDC), testability, constraints management and routing congestion analysis. Design groups use SpyGlass to verify that their design is ready to be handed off to back-end physical implementation tools. The Fast Lint methodology allows rapid feedback during the early stages of RTL development.  It is also used by revision control systems before new code check-in occurs.

“Last year, we introduced Advanced Lint at DAC to provide a highly detailed and accurate linting analysis,” said Mike Gianfagna, vice president of marketing at Atrenta. “Our customers told us they also wanted a fast capability during early RTL development. We listened, and this year we are introducing Fast Lint to provide our customers with both speed and accuracy.”

Atrenta will be demonstrating the entire SpyGlass and GenSys® product families in booth 2230 at the Design Automation Conference here at the Moscone Center in San Francisco from June 4 to June 6, 2012.  A new White Paper discussing linting methodology is also available from Atrenta and may be downloaded from the Resources area on the Atrenta web site.

About Atrenta

Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.

SpyGlass from Atrenta: Insight. Efficiency. Confidence.   www.atrenta.com

Leave a Reply

featured blogs
Jun 30, 2022
Learn how AI-powered cameras and neural network image processing enable everything from smartphone portraits to machine vision and automotive safety features. The post How AI Helps Cameras See More Clearly appeared first on From Silicon To Software....
Jun 30, 2022
The Team RF "μWaveRiders" blog series is a showcase for Cadence AWR RF products. Monthly topics will vary between Cadence AWR Design Environment release highlights, feature videos, Cadence... ...
Jun 28, 2022
Watching this video caused me to wander off into the weeds looking at a weird and wonderful collection of wheeled implementations....

featured video

Synopsys 112G Ethernet IP Interoperating with Optical Components & Equalizing E-O-E Link

Sponsored by Synopsys

This OFC 2022 demo features the Synopsys 112G Ethernet IP directly equalizing electrical-optical-electrical (E-O-E) channel and supporting retimer-free CEI-112G linear drive for low-power applications.

Learn More

featured paper

An Engineer's Guide to Designing with Precision Amplifiers

Sponsored by Texas Instruments

Engineers face many challenges when designing analog circuits. This e-book covers common topics related to these products, including operational amplifier (op amp) specifications and printed circuit board layout issues, instrumentation amplifier linear operating regions, and electrical overstress.

Click to read more

featured chalk talk

Single Pair Ethernet : Simplifying IIoT & Automation

Sponsored by Mouser Electronics and Analog Devices and HARTING and Würth Elektronik

Industry 4.0 with its variety of sensing solutions and fieldbus systems can make communication pretty tricky but single pair ethernet can change all of that. In this episode of Chalk, Amelia Dalton chats with representatives from three different companies: Analog Devices, HARTING and Würth Elektronik to discuss the benefits of single pair Ethernet, what the new IEEE standard means to SPE designs, and what you should consider when working on your next single pair Ethernet design.

Click here for more information about Single Pair Ethernet solutions from Analog Devices, HARTING and Würth Elektronik