News – Page 2013 – EEJournal

Synopsys and Samsung Deliver a Complete Solution for 20-Nanometer Node

June 5, 2012

MOUNTAIN VIEW, Calif., June 4, 2012 /PRNewswire/ — Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems today announced the availability of a complete solution to enable engineers to develop state-of-the-art System-on-Chip (SoC) designs at Samsung’s advanced 20-nanometer (nm) process geometry. The delivery of the solution is built on many years of close collaboration between Samsung Electronics and Synopsys R&D teams, including the tapeout of the first 20-nm chip based on Samsung’s High-k metal gate process technology. The double-patterning enabled solution includes Synopsys’ IC … Read More → "Synopsys and Samsung Deliver a Complete Solution for 20-Nanometer Node"

ams’ analog/mixed-signal foundry extends its customized IC test solution service

June 5, 2012

Unterpremstaetten, Austria (June 5, 2012), The Full Service Foundry business unit of ams (SIX: AMS) today announced an extension of its dedicated test solutions for its customers. This move is an extension of the company’s ”More Than Silicon” initiative, under which ams provides a package of intellectual property, cell libraries, consultancy and testing services to help customers successfully develop advanced analog and mixed-signal circuit designs based on its specialty technologies.

Foundry customers using ams’ IC test solution service will receive KGD (known good dies) and instantly gain the benefit of zero yield risk, as their complex analog/mixed-signal … Read More → "ams’ analog/mixed-signal foundry extends its customized IC test solution service"

Samsung and Cadence Deliver 20nm Digital Design Methodology

June 5, 2012

DAC Booth # 1930 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Samsung Electronics and Cadence have collaborated to deliver a 20-nanometer design methodology that incorporates double patterning technology for joint customer deployment and internal test chips. The collaboration between Cadence and Samsung brings new process advances for mobile consumer electronics, enabling design at 20 nanometers and future process nodes.

“With our focus on mobile consumer electronics, we needed a more efficient way to … Read More → "Samsung and Cadence Deliver 20nm Digital Design Methodology"

Parasoft Extends C and C++ Embedded Testing Support for Green Hills Software MULTI IDE

June 5, 2012

MONROVIA, CA and SANTA BARBARA, CA — June 5, 2012 — Parasoft Corporation, leader in helping organizations define and deliver defect-free software efficiently, and Green Hills Software, the worldwide leader in high assurance operating systems, announced today that Parasoft C/C++test, the industry’s most comprehensive testing solution for C and C++ development, now supports additional Green Hills Software MULTI® environments.

The latest release extends C/C++test’s integrated testing capabilities to embedded software engineers working with Green Hills MULTI compilers for V800, V850, and Linux x86 native. Green Hills MULTI users gain easy access to … Read More → "Parasoft Extends C and C++ Embedded Testing Support for Green Hills Software MULTI IDE"

IPL Alliance Announces IPL 2.0 and Appoints New Chair for Constraint Working Group

June 5, 2012

MOUNTAN VIEW, Calif., June 4, 2012 /PRNewswire/ — The Interoperable PDK Libraries (IPL) Alliance today announced IPL 2.0, an updated release of the semiconductor industry’s first open standard for interoperable Process Design Kits (iPDKs). The IPL 2.0 reference kit includes an iPDK developer’s guide, a sample 40-nanometer (nm) reference iPDK, a reference design and a user guide. It is ready now for validation by IPL Alliance members. In related news, the IPL Alliance appointed Ed Petrus from Mentor Graphics as the new chair for the IPL Constraint Working Group. In addition, the IPL Alliance will host its annual IPL Luncheon at the 49 … Read More → "IPL Alliance Announces IPL 2.0 and Appoints New Chair for Constraint Working Group"

Chip Path Design Systems Announces System-on-Chip Architectural Assembly and Floorplanning System

June 5, 2012

DESIGN AUTOMATION CONFERENCE, San Francisco, Calif. – June 4, 2012 –– Chip Path Design Systems, the system-on-chip assembly company, today announced that it will be showing a new system-on-chip (SoC) and application-specific integrated circuit (ASIC) architectural assembly and floorplanning system at DAC 2012 in San Francisco, CA. A unique feature of the new tools is the ability to graphically define and integrate architecture before beginning to hunt for vendor-specific intellectual property (IP). Chip Path has developed a model catalog of common I/O channels, subsystems, and connection networks used in SoC design.

“Everyone knows the parts that vehicles are designed … Read More → "Chip Path Design Systems Announces System-on-Chip Architectural Assembly and Floorplanning System"

ADLINK Launches Express-IBR with 3rd Generation Intel® Core™ Processors with Support for SuperSpeed USB 3.0 and PCI Express Gen 3

June 5, 2012

San Jose, CA – June 4, 2012 – ADLINK Technology, Inc., a leading global provider of ruggedized embedded products, announces the release of its latest Ampro by ADLINK™ Extreme Rugged™ COM Express® module, theExpress-IBR for airborne and vehicle-mounted military computers and human machine interfaces (HMI) applications required to function in harsh environments. The Ampro by ADLINK™ < … Read More → "ADLINK Launches Express-IBR with 3rd Generation Intel® Core™ Processors with Support for SuperSpeed USB 3.0 and PCI Express Gen 3"

Cadence Physical Verification System Qualified for TSMC 28nm, 20nm Process

June 4, 2012

SAN FRANCISCO, CA–(Marketwire – June 04, 2012) – DAC Booth # 1930 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that TSMC has qualified the Cadence® Physical Verification System (PVS) for 28-nanometer design signoff, and completed Phase I certification for TSMC’s 20-nanometer process.

Designers can request a PVS 20-nanometer technology file directly … Read More → "Cadence Physical Verification System Qualified for TSMC 28nm, 20nm Process"

Atrenta Introduces Fast Lint for SpyGlass®

June 4, 2012

SAN FRANCISCO, Calif — June 4, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced today at the 49thDesign Automation Conference (DAC) the availability of a Fast Lint methodology for its SpyGlass</ … Read More → "Atrenta Introduces Fast Lint for SpyGlass®"

Avnet Electronics Marketing and Digilent, Inc. Introduce the ZedBoard™, a Community-Based Development Kit for the Zynq™-7000 Extensible Processing Platform

June 4, 2012

PHOENIX— June 4, 2012 — Avnet Electronics Marketing, an operating group of Avnet, Inc. (NYSE:Read More → "Avnet Electronics Marketing and Digilent, Inc. Introduce the ZedBoard™, a Community-Based Development Kit for the Zynq™-7000 Extensible Processing Platform"