Aldec and Agilent Technologies Bridge the Gap Between ESL and RTL by Linking Simulation Environments
HENDERSON, Nevada – July 10, 2012 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions, worked with Agilent Technologies to deliver a new co-simulation interface between the latest version of Riviera-PRO™, Aldec’s popular design simulation and verification platform used by FPGA, ASIC, and SoC development teams, and SystemVue, Agilent’s ESL design and signal processing environment used by system architects and algorithm developers in physical layer designs of wireless, RF and DSP applications. The new solution enables users to … Read More → "Aldec and Agilent Technologies Bridge the Gap Between ESL and RTL by Linking Simulation Environments"

