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Imperas and Andes collaborate to support RISC-V innovations

Imperas reference models for Andes expanded with Andes Custom Extension™ support and design flow integration for leading EDA environments, plus new AndesCore® N25F-SE core for functional safety applications

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, has certified the Imperas reference models for the complete range of Andes processor IPs with Andes Custom Extension™ (ACE) support and the new AndesCore® N25F-SE targeted at Functional Safely applications. Developers can now use the Imperas reference models to evaluate multicore design configuration options for SoC architecture exploration, including custom instructions and full design flow integration with leading EDA tool environments.

Imperas models are often used in a ‘software first’ design flow that incorporates virtual-platforms / virtual-prototypes, as SoC developers explore new hardware configuration options with the application software workload and full OS supports. Traditionally, the use of virtual prototypes in a project for software development is a key piece of a company’s ‘shift-left’ strategy to accelerate schedules. Virtual prototypes shift schedules left by months because the models are available without the delays normally associated with implementations that are all dependent on the availability of a full RTL representation of the hardware. Now developers can also explore custom instructions with the Imperas models of the Andes cores utilizing the ACE framework.

The ability of virtual platforms to run the exact same binary code as the actual hardware also has advantages for complex system analysis and functional safety applications. Functional safety applications demand a high standard of system and software quality which in turn has implications for the project planning, tools and methodology. Functional safety is not just about resolving traditional software bugs and errors but also subjecting the entire platform to exceptional situations and functional stress conditions. This may involve complex combinations of external factors and internal operational modes of the device. Virtual platforms support both the analysis phase with control and visibility, and provide automation with integration into systems for CI/CD (Continuous Integration and Continuous Deployment). In functional safety applications, scenarios such as internal system failures and cascading event priorities can be simulated using virtual platforms with ease and repeatability to stress test the system that can be hard or event impracticable to achieve with physical prototypes.

“RISC-V represents the potential for innovation, and it is the implementation of great ideas that are really generating exceptional results,” said Dr. Charlie Su, President and CTO at Andes Technology Corp. “To unlock such potentials, Andes provides the AndeSysC™ environment, an extensible and near-cycle accurate SystemC model library for all AndesCore®. SoC architects can use it to construct a SystemC based virtual platform for performance evaluation of critical code segment and hardware/software co-optimization. ACE technology helps users implement custom functions and instructions, and it directly connects to the AndeSysC™ environment. Now with the close integration with the Imperas fast reference models and tools, design teams can embark on architecture exploration with complete application software for the next generation of domain specific devices with a seamless path to ACE implementation.”

“In any project the initial inspiration phase transitions to implementation. This is mirrored in the Imperas models for Andes cores that support both the architecture exploration and integration with Andes ACE for custom instructions,” said Simon Davidmann, CEO at Imperas Software Ltd. “Flexibility alone is insufficient for modern design flows as users depend on the established EDA tools and environments. The Imperas reference models cover the entire range of Andes cores and offer a frictionless path for users to explore the new design freedoms offered by the flexibility of RISC-V supported in all the major EDA environments.”

The Imperas reference models for the full range of Andes RISC-V processor IPs, including the latest N25F-SE, and the integrated support for ACE, is available now at:
Imperas RISC-V reference models are also available via approved EDA distribution partners. To explore this option in more detail, please contact Imperas or your preferred EDA supplier.

Andes RISC-V CON Silicon Valley
Imperas presented an update on the Andes certified reference models with ACE integration, including the support for popular EDA environments at Andes RISC-V CON Silicon Valley on October 18th 2022. Recording of the Imperas presentations are now available on YouTube.

Presentation: Architectural exploration for RISC-V optimized domain specific processors with Imperas and Andes ACE
Speaker: Manny Wright, Imperas Software Ltd
Recording now available on YouTube.

Panel: RISC-V Ecosystem panel: From Edge to Cloud
Moderator: Daniel Nenni, Founder, SemiWiki
Panelist: John Min – Andes, Chris Jones – Crypto Quantique, Max Hinson – Green Hills, DeWayne Gibson – IAR, and Katherine (Kat) Hsu – Imperas
Recording now available on YouTube.

RISC-V Summit 2022
Imperas is proud to be a contributing Diamond sponsor for the fifth annual RISC-V Summit, December 12-15 2022 in San Jose, California. Imperas will showcase solutions for RISC-V processor verification, custom instruction design flows, and software development, including a keynote on RISC-V Processor verification plus many other activities.
For more information, please visit RISC-V Summit 2022.

About Imperas
Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open-source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at and the Open Virtual Platforms (OVP) website at

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