MOUNTAIN VIEW, Calif., June 14 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today introduced its Galaxy Characterization Solution. The Galaxy Characterization Solution is a comprehensive suite of tools architected to generate compact, highly-accurate libraries for the design and implementation of complex system-on-chips (SoCs). Today’s SoCs require libraries that contain hundreds of gigabytes of timing, power, noise and process variation data to ensure the chip meets all performance criteria. The Galaxy Characterization Solution is the only solution that can reduce the library size by an average of 4X and deliver precise timing, noise and power models for standard cells, macros and memories in the compact composite current source (CCS) library format.
The Galaxy Characterization Solution is based on Synopsys’ golden-accuracy HSPICE® circuit simulation, technology-leading StarRC(TM) extraction, NanoTime transistor-level timing and Liberty™ NCX library modeling technologies. The compact CCS models generated by the solution feed seamlessly into the IC Compiler physical implementation and PrimeTime® signoff tools, enabling designers to quickly achieve timing closure and improve productivity.
As process geometries shrink to 28 nanometers (nm) and below and clock frequencies rise, it is essential to account for signal integrity (SI) and variation effects in the timing and noise model libraries to ensure proper silicon performance. As a result, library sizes can quickly explode from tens of gigabytes to hundreds of gigabytes. This poses a dilemma for the designer who needs accuracy but can’t handle the enormity of the library or a potential increase in run time. To address this, Liberty NCX generates a compact CCS model that can reduce the library size by an average of 4X without impacting accuracy. In addition, Liberty NCX has been tuned for noise model generation, resulting in up to a 7X speedup. PrimeTime and IC Compiler readily process the compact CCS format, saving valuable run time, disk space and, ultimately, engineering costs.
“Synopsys’ unique combination of technology and innovative methodologies enables the Galaxy Characterization Solution to deliver a comprehensive characterization capability that covers all aspects of designers’ needs,” said Dr. Antun Domic, senior vice president and general manager, Synopsys Implementation Group. “High-precision compact CCS models for power, timing and noise, combined with the seamless handoff to PrimeTime and IC Compiler allow designers to implement their SoC designs with a high degree of confidence.”
Today, the Galaxy Characterization Solution supports timing, power and noise models for standard cell libraries. Upcoming releases will provide timing and noise models for complex macros and embedded memories and will employ the NanoTime static timing engines to generate the results.
About Synopsys
Synopsys, Inc. (NASDAQ:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.
