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RISC-V Foundation’s Chairman says: “All Your Cores Are Belong to Us”

When RISC-V International’s chairman of the board Krste Asanović took the stage to report on the state of the RISC-V union at last month’s RISC-V Summit, he mouthed the phrase that’s always said by the president of the United States when reporting the country’s state of the union: “The state of the union is strong.” Later in his talk, Asanović said the same thing, but in a much more assertive way: “All your cores are belong to us.”

RISC-V International’s chairman of the board Krste Asanović.
Image credit: RISC-V International

I thought that Asanović’s comment was hilarious, but I didn’t hear much reaction to that phrase coming from the RISC-V Summit audience. Perhaps the crowd was too young to get the joke, so in case that Internet meme is too old for you, it’s based on a bad English translation of the original Japanese dialog in the video game “Zero Wing,” which started as an arcade game and then was ported to the Sega Mega Drive (Sega Genesis in the US) home video game console. One line in the dialog has the alien villain, CATS, says “All your base are belong to us.” This meme became firmly cemented in my consciousness, thanks to a YouTube video like this one:

Besides being RISC-V International’s chairman of the board, Asanović is a Professor of EECS at UC Berkeley, and he’s also a co-founder of RISC-V core vendor and the company’s Chief Architect. Clearly, he’s somewhat partisan when it comes to RISC-V. Asanović started his “State of the Union” presentation with what he called a “public service announcement.” In this announcement, he echoed three bullet points presented earlier in opening remarks made by RISC-V International’s Calista Redmond. The three points are:

  • RISC-V is inevitable
  • RISC-V will have the best processors
  • RISC-V will have the best ecosystem

There’s no question that the RISC-V microprocessor ISA has a large and growing community. RISC-V International’s member count has passed 3000 organizations and individuals. Because RISC-V is a large and growing force in the microprocessor, microcontroller, SoC, and FPGA arenas, I think it’s worthwhile for EEJournal to take a critical look at these three claims.

Let’s start with Asanović’s and Redmond’s claim of RISC-V’s inevitability. Asanović used the analogy of Ethernet’s eventual rise and complete dominance in networking. He pointed out that there were many competing networking standards in the early 1980s including DECnet, IBM Token Ring, AppleTalk, Acorn Econet, ARCNET, FDDI, etc. Most of those networking standards eventually fell to Ethernet, which is true., I remember writing an article back in the 1980s about industrial networks such as FieldBus and MAP (the Manufacturing Automation Protocol) that General Motors planned on using in its factories. All these networks have fallen to the inevitability of Ethernet.

Even in arenas like the automotive market, vehicle-centric networks like the CAN bus are yielding to Ethernet. In every case where there’s sufficient commercial volume, and even in some places where there is not, the Ethernet community has added the needed features to the growing body of Ethernet standards whenever needed to supplant other networking standards. For example, Ethernet fell well short of meeting the timing needs of deterministic, real-time systems, so the IEEE developed a set of standards called TSN (time-sensitive networking) to bridge this capability shortfall.

However, I think this is a flawed analogy to use for RISC-V. Interoperability is essential for networking. That’s the entire reason that other competing networking schemes shrank into oblivion. Myriad systems from different vendors simply must use the same networking protocols if they are to interoperate with each other. The same cannot be said for microprocessor ISAs (instruction set architectures). We have decades of experience in making systems based on how different processor ISAs interoperate with each other. The RISC-V ISA is truly flexible and has a very broad footprint when it comes to processor ISAs, but I cannot agree that it will consume the market as Ethernet has done for four decades.

Even though Asanović’s networking analogy doesn’t work for me, his assertion that the industry wants an open-standard ISA business model rings quite true, as validated by RISC-V International’s growing membership list. This momentum alone validates Asanović’s and Redmond’s assertion that RISC-V is inevitable, although it hardly proves that the RISC-V ISA will be the only ISA in the future. Processor architects love to design new processors with new ISAs – after all, that’s their job, by definition – and the existence of the RISC-V ISA isn’t going to dampen their enthusiasm any more than the existing x86 and Arm ISAs. The obvious target for RISC-V is Arm, which has established its multiple architectures in myriad markets. RISC-V proponents aspire to do the same.

Nevertheless, undeniably real factors drive the desirability of a universal processor ISA, preferably one based on an open standard. In my opinion, the strongest factor driving the adoption of the open RISC-V ISA is the desire to see far more competition in the microprocessor IP core market based on a common – although not necessarily even – playing field. Many IP vendors are creating microprocessor cores based on the RISC-V ISA, and their cores span the performance spectrum from simple microcontroller cores with implementations ranging from 3-stage pipelines to massively large server-class cores with multiple and deep execution pipelines and out-of-order (OOO) instruction execution.

Several of these core vendors announced new cores at the RISC-V Summit, proving the vibrancy of the market. For example, Asanović presented a slide that listed RISC-V IP core and chip vendors competing at the high end of the market with OOO processors and cores. The non-exhaustive list included Alibaba, Andes, Esperanto, Rivos, Semidynamics, SiFive, Tenstorrent, and Ventana. That list omitted MIPS, which announced an OOO RISC-V core called the eVocore P8700 at the RISC-V Summit.

This long list of high-end microprocessor core vendors competing in a similar space gives credence to Asanović’s second assertion, that RISC-V will have the best processors. With so many vendors competing, the best architectural ideas will likely rise to the top and will strengthen all RISC-V cores as the ideas permeate the growing RISC-V community.

Asanović predicted a truly broad market for RISC-V cores, saying that the modular and extensible ISA would be used to create:

  • Applications processors
  • Graphics processors
  • Image processors
  • AI/ML accelerators
  • Radio DSPs
  • Audio DSPs
  • Security processors
  • Power-management processors

That prediction doesn’t take much of a leap of faith. Someone somewhere is surely using the RISC-V ISA to develop every type of processor on that list already. One of the attributes that make RISC-V attractive as a universal ISA for all these processor types, said Asanović, is a uniform, high-quality software stack supported by the growing RISC-V community. Instead of fragmenting software support across diverse ISAs for all these processor types, the RISC-V ISA unifies the software tool chain including compilers, debuggers, trace tools, and performance analysis tools.

Asanović believes that these attractive attributes will end what he called the Balkanization of processor ISAs. I think the jury is out on this point. Processor architects seem to thrive on ISA Balkanization. Witness the divergence in x86 optimizations driven by AMD and Intel. I think it’ll be a hard habit for the industry to break, regardless of RISC-V International’s efforts to prevent this.

The final point in Asanović’s public service announcement was the aspirational prediction that RISC-V will have the best ecosystem. Certainly, that’s not yet reality. The RISC-V ecosystem is growing, but it’s not yet mature. Even Asanović admitted that this assertion seems hard to believe at the moment. He admitted that there are gaps in the ecosystem to fill. For example, Android has yet to be ported to the RISC-V ISA, although that project is already underway. There’s no technical reason why Android can’t run on a RISC-V processor. Whether all of the apps developed for Arm-based Android systems will cross over easily, or at all, remains to be seen.

Asanović’s final points were that RISC-V hardware and software have been co-evolving, which strengthens the ISA, and that some long-running IP core and silicon development projects are starting to bear fruit. Certainly, the many new product announcements at the RISC-V Summit confirm that last statement. “There’s no reason that processors based on the RISC-V ISA can’t be as fast as or faster than any processors currently on the market,” said Asanović. “It’s just a matter of time, energy, and motivation.” Then Asanović concluded, “RISC-V is going to be everywhere. Once you go from proprietary [standards] to open source, you don’t go back.” That part of the Ethernet analogy rings true.

For my previous RISC-V coverage in EE Journal, see:

RISC-V Aims for World Domination

Fifty (or Sixty) Years of Processor Development…for This?

RISC-V Business: RISC-V Evolves from Academic Teaching Platform into a Major Microprocessor Player

Intel Foundry Services (IFS) Appears To Go All In On RISC-V

Machine Learning: Esperanto coaxes 1092 RISC-V Processors to Dance on the Head of a Pin, er Chip

Microsemi Joins RISC-V Love Fest with SoC FPGA

Note: If you’re interested in the full history of “All your base are belong to us,” the definitive history of this early Internet meme can be found in this YouTube video:


One thought on “RISC-V Foundation’s Chairman says: “All Your Cores Are Belong to Us””

  1. Well this just ruins my day!
    I was lead to believe all the crap about free and open!

    Now I find out it ain’t mine after all, the almighty just letin’ me use it.

    I suppose RISC-V went from teaching platform to Computer Cum Laude with honors.
    If you look under the hood, what do you see? An instruction register/decoder, data registers, ALU, comparator, and whatever it takes to interface with memory/cache. i.e. address, data in/out, request/select.


    Show me sumthin’ new, dammit!

    I have something new: aka BDL. Boolean/Block DESIGN Language. So old fashioned, design it first then describe it in a way that can be built. ALL OF IT, NOT JUST WHAT CAN BE SYNTHESIZED!

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