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Welcome to a World of Reconfigurable Intelligent Surfaces

Have you heard that the European Telecommunications Standards Institute (ETSI), which produces globally applicable standards for Information and Communications Technology (ICT), recently launched a new Industry Specification Group on Reconfigurable Intelligent Surfaces (ISG RIS)?

There’s no need to hang your head in shame if this is new news to you. To be honest, I didn’t even know that ICT was an abbreviation for “information and communications technology” until now (well, I’m sure I knew it once, but it’s easy to lose the thread if you don’ … Read More → "Welcome to a World of Reconfigurable Intelligent Surfaces"

How the FPGA Came To Be, Part 5

As discussed in Parts 1 through 4 of this article series, the earliest PLDs evolved along easily traced genetic lines that started with Harris Semiconductor’s programmable diode arrays from the 1960s and progressed through bipolar PROMs, the Signetics 82S100 FPLA, MMI’s PALs, and finally the transcendent CMOS replications of PAL devices created by Altera and Lattice Semiconductor. By contrast, FPGAs (called “Logic Cell Arrays” in the first press release) came from a similar concept, field-programmable logic, but from an entirely different direction.

While working at microprocessor pioneer Zilog … Read More → "How the FPGA Came To Be, Part 5"

When Reliability Analysis Meets Silicon Lifecycle Management

I’ve recently been chatting with folks from Synopsys and Concertio, and now my head is so full of “stuff” regarding things like hyper-convergent chip design, reliability analysis, real-time performance optimization, and silicon lifecycle management that I don’t know whether I’m coming or going.

I’ve told this tale before (and I’ll doubtless tell it again), but when I worked on my first digital ASIC design circa 1980 at International Computers Limited (ICL) in Manchester, England, the only design tools I had at my disposal were pencils, paper, … Read More → "When Reliability Analysis Meets Silicon Lifecycle Management"

How the FPGA came to be, Part 4

By the end of the 1970s, PALs had become the PLD (programmable logic device) of choice for system designers. They were an immensely successful product for Monolithic Memories Inc (MMI). They were also a great target for every other IC maker that wanted to enter the PLD arena. Several did just that. 

Bob Hartmann co-founded Source III in 1980. The consultancy specialized in the design of gate arrays, because the early 1980s was definitely a golden time for gate-array development. The major gate-array vendors of … Read More → "How the FPGA came to be, Part 4"

How the FPGA Came To Be, Part 3

Part 2 of this article series discussed the development of the first successful programmable logic device, the Signetics 82S100 FPLA (field programmable logic array). A Signetics salesperson tried to convince John Birkner, a minicomputer designer at Computer Automation in Irvine, California, to use the 82S100 in his designs, but Birkner saw that the device was too costly, too big, and too slow. He thought he should go to Silicon Valley to set the IC vendors straight.

John Birkner soon got the chance to “go up there and tell them … Read More → "How the FPGA Came To Be, Part 3"

Multifarious Multifaceted Memory Solutions for AI, ML, and DL

I recently had a very interesting chat with Steven Woo, who is a Fellow and Distinguished Inventor at Rambus. I’d like to kick off by saying that Steven is a delight to talk to. He’s obviously got a size-16 brain (one of the sporty models with “go-faster” stripes on the side), but he’s so good he ends up making you feel clever (as opposed to so many people who make me feel like an… I was going to say “ignoramus,” but I don’ … Read More → "Multifarious Multifaceted Memory Solutions for AI, ML, and DL"

How the FPGA came to be, Part 2

Part 1 of this article series discussed the earliest programmable ICs that could be used to implement logic circuits. Not quite programmable logic, Harris Semiconductor’s programmable diode arrays and PROMs laid the groundwork for PLDs (programmable logic devices) to come.

This is where we return to Napoleone Cavlan, Ronald Cline, and the story of how Signetics developed the first commercially successful FPLA (field programmable logic array). Cline and Cavlan both had memory IC design experience and both joined Signetics at just the right time to participate in the … Read More → "How the FPGA came to be, Part 2"

Next-Gen Voice Interfaces for Smart Things and Loquacious Folks

I was just chatting with Mark Lippett, who is CEO at the British chip company XMOS. Mark was telling me that they recently announced the launch of their XVF3610 and XVF3615 voice processors. These little beauties will power the next generation of high-performance two-microphone voice interfaces for wireless speakers, TVs, set-top boxes, smart home appliances, gateway products, and more. We will be talking about these in greater detail in a moment, but first…

Let’s start by reminding ourselves that Read More → "Next-Gen Voice Interfaces for Smart Things and Loquacious Folks"

How the FPGA Came to Be, Part 1

I started designing engineering workstations in 1981 for Cadnetix in Boulder, Colorado. The top computer-aided engineering (CAE) vendors of the day – Daisy Systems, Mentor Graphics, and Valid Logic (I called them the DMV) – were all founded in 1981, like Cadnetix, and each developed their own proprietary CAE software suite. The five proprietary Cadnetix workstations that I helped to design, introduced from 1982 to 1985, were all based on versions of Motorola Semiconductor’s 68000 microprocessor family (the 68000, 68010, and 68020) running a proprietary, stripped-down version of Unix (which I privately called Eunuch as an inside joke).

Daisy’ … Read More → "How the FPGA Came to Be, Part 1"

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Mar 20, 2026
From machines that see and think, to systems that act, and the humans that nudge them along....