FPGAs fall into two distinct camps – high-performance and low-cost. For several years, the rules and conventions of these strata have been established and followed by FPGA companies. Low-cost or value-based FPGAs are designed with cost as the first priority. Every spare feature is thrown overboard in order to minimize die size and production cost, leading to the lowest possible price-per-LUT for a given amount of programmable fabric. High-end FPGAs, on the other hand, spare no expense in offering the maximum performance and the richest feature sets.

The silicon selection rules for FPGA designers have been, therefore, rather easy to understand. If you have a high-volume, cost-sensitive application, you go for the value-based FPGA. If you need advanced features like DSP blocks, super-fast clock speeds, and the queen of all high-end features – SerDes transceivers, you popped out the checkbook and went for the exotic high-performance families. It was unambiguous. You were in either group A or group B. There was no middle ground.

In FPGA marketing departments, the official Venn diagram was two separate circles with no overlap. This made PowerPoint slides much easier, as you could draw your target market with only two colors. Unfortunately, though, although simple from a PowerPoint perspective, this left some design teams out in the cold. What if you had a high-volume, cost-sensitive application that happened to require some level of SerDes capability – not necessarily your super-duper, double-digit gigabit, suitable for connecting the heart to the brain kinda’ SerDes, but something more modest like, say, PCI Express, or Gigabit Ethernet? You were, it turns out, lost in that missing third color region of the Venn diagram – ignored – bitmapped out of the FPGA market.

Your options in those situations were fairly limited. If your volume was big enough and nobody really cared when your project was finished, you could dish out some impressive NRE and go for an ASIC implementation. SerDes, however, put you immediately in the moderate-to-exotic ASIC range, so you were looking at a challenging design project. If you really needed programmable logic, you could try mating up a low-cost FPGA with an external SerDes PHY. For some designs, that gave an adequate solution. The downside to that approach, however, was more complex memory architecture, chip-to-chip interface issues, and a larger BOM.

This week, Lattice Semiconductor found that phantom third color. Their newly announced ECP2M family is a 90nm low-cost FPGA platform with a few additional goodies not found on the regular low-cost menu. They’ve basically taken their already successful low-cost 90nm ECP2 platform, added SerDes transceivers, and boosted RAM to the required level for most SerDes-streaming applications. Combined with the already-announced DSP blocks, this product line has now clearly stepped over the line and broken the rules for low-cost FPGAs.

Yes, we see a hand in the front row? We wondered the same thing. What keeps the cost down on a low-cost FPGA when you start adding so many of the features usually found only in high-end programmable platforms? It turns out Lattice has been very judicious in their feature selection, targeting only specific capabilities to enable common applications in order to keep costs down. For example, SerDes transceivers in FPGAs can get very complicated (and therefore expensive) because a single type of transceiver has to be able to support a wide variety of rates and protocols. In order to keep area down and yield up, Lattice has narrowed the focus of their SerDes – supporting 3Gbps and protocols such as PCI Express and gigabit Ethernet. By trimming off all the bells and whistles required to support the broader range of SerDes styles, Lattice made a conscious decision to focus for cost reduction. Other factors like packaging options contribute to cost control as well, with the result being an FPGA family that aims squarely at the missing masses in the low-cost/high-performance market model.

The new ECP2M family weighs in with LUT count ranges between the typical low-cost and high-end zones – 19K to 95K LUTs. Lattice has boosted the memory capacity considerably as well, with block RAM ranging from 1.2Mb to 5.3Mb, and distributed RAM from 41K to 202K. For number crunching, the new family has from 24 to 168 18X18 multipliers built into its DSP blocks, and it carries significantly more clocking resources than its ECP2 cousins with 8 PLLs and 2 DLLs in each family member. On the I/O front, ECP2M packs from 4 to 16 SerDes transceivers. These transceivers offer data rates from 540Mbps to 3.125Gbps. In addition to the aforementioned PCI Express and gigabit Ethernet, they also support Serial RapidIO and SGMII. The family also has user I/O ranging from 144 to 601 user I/O pins with support for DDR1 and DDR2, which will come in handy for bolting on all that external RAM.

Lattice also has continued their extremely flexible configuration support with ECP2M. In addition to conventional SPI boot memory and jtag-based configuration support, Lattice also offers 128-bit AES encrypted bitstream for security-sensitive applications. There are also available options for automatic dual-boot configuration for fail-safe during field upgrades, and an in-operation field configuration that allows I/O states to be defined during a reconfig operation.

In going after the PCI Express market in particular, Lattice has pre-packaged a demo board and development system specifically aimed at accelerating development of PCI Express applications. The board comes in a PCI Express Plug-in card form factor and includes X1 and X4 cores, a GUI-based configuration for X1 and X4, and software drivers to jump-start system-level integration. This sort of out-of-the-gate domain-specific development kit shows that Lattice has done their marketing homework and is aiming the new family at fertile new ground in the FPGA market.

Keeping up with their practice of short lead-time introductions (and going against another industry trend in the process), ECP2M samples in October with production release planned for Q4 ’06. Lattice estimates pricing at about $0.65 to $1.00 per KLUT in volume – so we’re talking prices that run the double digit dollar gamut. As an example, they say that the ECP2M35 (35K LUT) device in a 484 fpBGA package could be as little as $22.95 at 100K units in 2007. At those prices, developers of PCI Express applications in particular will be very interested in the capabilities of this device.