Before FPGAs became viable system-on-chip platforms, there were two simple basic food groups in the embedded processor world: stand-alone processors for board- and module-level integration and processor IP cores for system-on-chip integration. Some of the most successful offerings today are processor architectures that managed to span both of those domains, such as ARM’s wildly successful architectures that have attained widespread adoption both as flexible IP cores in ASIC SoC implementations and in high-value, stand-alone chipsets for board-level integration.
Recently (as we’ve thoroughly documented in these pages), FPGAs have shrunk and grown to the point that they, too, are viable options for system-level integration. When we hit the point that an FPGA could house a reasonable 32-bit processor capable of running an OS or RTOS, enough peripherals to construct a useful machine, and enough memory to run an interesting application, we entered a new era of embedded processing options.
The situation with FPGA-based processors is unique, however, with several factors separating the new environment from the existing mainstream. First, early attempts at embedding hard processing elements in FPGA families failed, as none of the players managed to mix a chip that offered on-chip processing power matching what could be added externally for less money. Soft-core processors tended to be preferred because of their greater degree of flexibility and because they didn’t increase the cost of devices for applications where a processor was not needed.
Traditional embedded-processor powerhouses such as ARM and MIPS shied away from creating soft-core versions of their products for FPGA implementations, presumably in part because performance is difficult to achieve in such a design, and also because processor IP is much more difficult to protect in a soft-core-based design flow. Market dominant suppliers Xilinx and Altera each created their own proprietary processor offerings, making the decision to accept a tougher adoption curve in exchange for saddling customers with an IP block that tended to lock their design into that particular FPGA vendor’s devices.
With Xilinx and Altera pushing their MicroBlaze and Nios soft cores, always alternative supplier Actel countered with a groundbreaking deal with ARM where soft versions of ARM7 processors could be dropped securely into Actel’s non-volatile flash-based FPGAs. Because their basic products have significantly different characteristics from mainstream SRAM-based FPGAs offered by the two large suppliers, however, the ARM-based Actel products tend to compete in different markets from Xilinx’s and Altera’s products.
The past two years, however, Lattice Semiconductor has been launching an all-out assault directly at the two big players. Rather than taking Actel’s approach of choosing an alternative architecture that might appeal to different markets, Lattice went head-on at Xilinx and Altera with product lines that matched one-on-one with the big boys, but differentiated themselves at the specific feature level.
Now, in creating their soft-core processor product, Lattice has continued that strategy. Like Xilinx’s MicroBlaze and Altera’s Nios, Lattice’s new Mico32 is a soft-core RISC processor that can be easily dropped into an FPGA. Unlike the others, however, Mico32 is completely open. Rather than take the lock-’em-in approach of their competitors, Lattice has gone the open source route, cleverly betting that enabling processor-based designs on their devices was much more important than locking customers into their architecture with an IP core.
LatticeMico32 uses fewer than 2,000 look-up tables (LUTs) on an FPGA, which makes it a very inexpensive engine for your embedded design. Because the processor is soft, you can configure it with just the options you want for your application. Optional features include things like data and instruction caches, user-defined instructions, and multipliers. This kind of application-specific customizability as well as the flexibility to add any number of processors to your design with only a small area penalty is the kind of flexibility that has made FPGA-based soft cores so popular among designers. Mico32 weighs in with 32 general-purpose registers, up to 32 external interrupts, and a dual Wishbone memory interface. Lattice estimates that the processors can run at over 100MHz on their low-cost 90nm ECP2 FPGAs.
In keeping with the open-source approach, Lattice chose the public domain Wishbone bus interface for Mico32 and has already announced a variety of available peripherals, including memory controllers, asynchronous SRAM, on-chip block memory, I/O ports, a 32-bit timer, a DMA controller, general-purpose I/O (GPIO), an I2C master controller, a serial peripheral interface (SPI), and a UART. These plug-on peripherals dramatically speed up system design, eliminating the need to custom-code many of the common hardware functions if you’re building a Mico32-based embedded system.
One of the most important enabling features for any embedded processor is the compatible development system. Lattice has again followed the open-source philosophy with an Eclipse-based C development tool suite for software. The hardware side of the implementation follows Lattice’s established ISPLever flow, fronted by Mico System Builder (MSB). MSB allows configuration of the processor and peripherals and passes the information on to Lattice’s hardware implementation tools. Lattice has already announced development kits that include development boards with a variety of interfaces, peripherals, and software development tools.
When Lattice says the new core is open-source, they’re serious. They’ve put the generated HDL code for the processor as well as selected peripherals into open source, and the cores are free to use. Hardware utilizing the cores can be freely distributed without license documentation. The software development tools, including compiler, assembler, linker, and debugger, are also open source – licensed under the GNU General Public License (GPL). This open approach should accelerate adoption of the new cores as well as encouraging public participation in enriching the ecosystem for the new processor. Lattice’s model even allows the processor to be taken to non-Lattice platforms such as ASICs, structured ASICs, and even presumably other types of FPGAs. This ability to standardize on a processor architecture without locking yourself into a particular hardware technology will probably be welcomed by many development teams.
One thing not yet making an appearance is OS support for Mico32. If we had to guess, we’d predict that an embedded Linux connection would be coming soon. We’d also predict connections to other popular embedded operating systems, but we’ll just have to wait for Lattice to feed us additional details as they emerge.
