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What’s Your Persona?

Unbelievable! FPGA Journal is running a feature article on a Xilinx organization change? What’s next, an exposé on Altera’s new carpets at corporate headquarters? Maybe an in-depth analysis of Lattice’s motivation for switching from Seattle’s Best to Stumptown coffee in their cafeteria? What happened to the concept of discriminating technical journalism?

While org-chart changes are certainly not our typical subject matter, we’re not just talking about a few ambitious executives forging a path up the corporate career ladder. We won’t repeat the details from … Read More → "What’s Your Persona?"

Jason Cong

Professor Jason Cong’s office on the campus of UCLA is full, but not cluttered; important, but not pretentious; functional, but not over-designed. A wall of bookshelves that overlooks the desk and conference table is filled with proceedings from probably every technical conference ever to approach the subject of programmable logic design. One gets the impression that Professor Cong has not only read them all, but also participated in the production of a good percentage of them.

There is nothing in particular here to tip the casual visitor that this is the dojo where much of … Read More → "Jason Cong"

Methodology Melting Pot

The first explorers came with Karnaugh maps and truth tables. Complex combinational functions could be concentrated in programmable logic devices more efficiently than with random logic parts or large, sparse ROMs. As these early PAL pioneers blazed trails into a new frontier of logic design, a culture of design methodology grew around them, and the process refined itself with design automation tools and techniques tailored to their needs.

Over time, programming PALs became less and less exclusive. The problems and pitfalls faced by early designers were known and solved, and automation techniques relegated programmable logic … Read More → "Methodology Melting Pot"

Advancing FPGA Design Efficiency: A Proven Standard Solution

For decades the SoC design community has consistently lost ground in the battle to match advances in design technology productivity with the growth of available silicon technology. The silicon evolution roadmap has long been chronicled via Moore’s law, so how could the design community allow the existence of the well-known “Design Gap?” Understanding how we got to this point will make it easier to answer that question and make reasonable adjustments for the future, especially if there are obvious things to be learned from the evolution of many analogous industries.

Even in the … Read More → "Advancing FPGA Design Efficiency: A Proven Standard Solution"

Digital Do-Overs

His eyes meet the goalie’s steely gaze. He refuses to be stared down. In his mind, he calmly visualizes the moves to come, picturing success at each step. He will take three measured strides before his right foot strikes the ball slightly below center. He will follow through with his leg and keep his eyes riveted to the goal as the penalty kick tracks an arcing path through the air, catching the upper right corner of the net just out of the goalie’s reach. He exhales and begins the carefully choreographed sequence. As he nears … Read More → "Digital Do-Overs"

FPGA I/O Features Help Lower Overall PCB Costs

Introduction

High-end FPGAs with embedded processors, DSP and memory blocks are now replacing entire ASICs. New device families have accelerated programming times by dedicating several general-purpose I/O pins to create wider configuration buses that can then revert back to their primary I/O functionality. Rising device complexities imply high pin counts, which bring about new challenges and added costs when integrating these devices on the PCB. Design teams must now implement changes to ensure they do not negate the cost and time-to-market benefits of using programmable logic in the first place.

< … Read More → "FPGA I/O Features Help Lower Overall PCB Costs"

FPGA I/O

Over the past decade, FPGAs have gained a foothold as one of the most used building blocks in digital systems. The flexibility of an FPGA allows designers to decrease hardware design cycles while adding inherent feature upgradability in the final product. In addition, the data rates of modern FPGAs are competing with CMOS ASICs, thus allowing the needed system performance to be achieved using what was … Read More → "FPGA I/O"

FPGAs in Space

When was the last time you disassembled the package of each FPGA in your design to make sure the bonding is secure? Would your design criteria be different if shipping your device to its destination cost $13,000.00 per pound? What if your FPGA was in an environment where the radiation levels made random upsets of memory elements more the rule than the exception? If your device were operating in a vacuum, how would you think about heat dissipation? Would you work or think differently if an error in your design could result in loss of life, or in property damage … Read More → "FPGAs in Space"

The Challenges of Modern FPGA Design Verification

Fifteen years ago verification of FPGA designs was easy: you only needed a decent gate-level simulator to verify a circuit containing several thousands of logic elements. As the size of FPGAs started to grow, so did the complexity of the designs implemented in them.

Over time, hardware description languages sneaked into schematic designs and eventually replaced schematic entry.

Today, it is quite common that FPGA users have to deal with more than one language in their designs (e.g. original sources in VHDL with some IP core in Verilog). At earlier stages of the design … Read More → "The Challenges of Modern FPGA Design Verification"

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