The concept of clocking a register is pretty simple. It’s Logic Design 101 stuff. Having an entire system controlled by a uniform clock makes accessible that which would otherwise be an intractable problem. It’s like adding traffic lights downtown to keep traffic from getting completely chaotic.

A whole discipline has grown out of this very basic concept: that of synchronous design. An entire ecosystem of tools and techniques has been built around some very fundamental assumptions of how to design such circuits. And as the circuits have gotten bigger, clock tree synthesis (CTS) has … Read More → "Skew This!"

When it comes to system-on-chip verification, two trends have become painfully obvious: it is expensive and it takes too long. Consider, for example, that the most expensive parts of today’s SoC design flow are the tasks where the engineer must engage in direct manual effort or expend energy making decisions. In the case of verification, far too much time and money are wasted on tasks that don’t add value, such as trying to figure out how supposedly-correct intellectual property (IP) is actually working, debugging “dumb” errors or deciding what signals to record in … Read More → "Visibility Enhancement Technology Confronts the Visibility Issue with Full-Chip Simulation"

Design For Manufacturing (DFM) was a headline darling for a while and somehow disappeared off the radar, even as debates continued as to whether all the DFM fuss was about nothing. In fact, much of what constitutes DFM, originally implemented as point tools by young upstart companies, has quietly been subsumed into mainstream flows by mainstream tool providers, thanks in part to the traditional EDA start-up/buy-up cycle.

Fundamentally, design and verification have gone from modeling the idealized results of a manufacturing process to modeling the actual manufacturing steps in much greater detail. The criticality and accuracy … Read More → "Dueling DFMs"

Wall Street says, “Flat is the New Up!” GSA says, “Semiconductor sales for 2008 totaled $252 billion and dropped 6%, compared to 2007 sales of $268 billion.” California’s unemployment rate hit a record 11.2 percent in March 2009, allegedly the worst since the Great Depression! In our own world, EE Times reports: “The unemployment rate for all engineers jumped from 2.9 percent in the fourth quarter of 2008 to 3.9 percent in the first quarter of 2009, IEEE said.” And Nostradamus predicted the end of the world… For businesses, it’s all about increasing productivity, maximizing ROI, accelerating time to market, … Read More → "Demonstrating Targeted ROI"