Wall Street says, “Flat is the New Up!” GSA says, “Semiconductor sales for 2008 totaled $252 billion and dropped 6%, compared to 2007 sales of $268 billion.” California’s unemployment rate hit a record 11.2 percent in March 2009, allegedly the worst since the Great Depression! In our own world, EE Times reports: “The unemployment rate for all engineers jumped from 2.9 percent in the fourth quarter of 2008 to 3.9 percent in the first quarter of 2009, IEEE said.” And Nostradamus predicted the end of the world… For businesses, it’s all about increasing productivity, maximizing ROI, accelerating time to market, and reducing risk. The stakes are higher than ever in this economy.
Chip designers worldwide have told Jasper that they’re looking for something fundamentally different to help them with their technical and business problems. We’ve coined the term “Targeted ROI” to describe the process: customers start at the top, looking at key verification challenges – from getting their architectures unambiguously right, to putting more power in the hands of designers, to promoting design reuse, to verifying critical functionality, to reducing process bottlenecks…even silicon debug! We then collaborate to determine where verification solutions can be applied, and to evaluate the return on investment. Our experience is that pre-qualifying ROI for project objectives has been a key contributor to successful tool proliferation, even during a sagging economy.
To best illustrate these concepts in practice, let’s examine a few real-world challenges:
Architectural verification: Uncovering architecture-related problems early prevents costly re-design. For example, it’s practically infeasible to get sufficient coverage at the design level for cache-coherency protocol checking.
RTL design and debug: Reduces overall engineering effort by allowing RTL designers to debug their own code, reducing the need for simulation and downstream verification effort often by a factor of 3 to 1.
Proofs of critical functionality: Arbitration, control, protocols, busses and high-level block behavior are complex behaviors that simulation alone is not equipped for. Formal verification simplifies proofs of correctness, and helps to visualize and solve for many complex mode-dependent behaviors.
SoC integration: Connectivity issues can be time-consuming with conventional methods, and delay chip-level integration. Formal technology automates and accelerates problem formulation, analysis, and debug.
Design reuse: This is the mantra for productivity, and is clearly the wave of the future. We have expanded our offerings to include design services to help companies develop blocks for design re-use, accelerating deployment of those blocks in other designs, both later in time, and across geographically widespread design groups.
The examples above can be quantified for various types of Targeted ROI including time to market, risk and required resources. In this way, our customers are able to clearly visualize the value proposition for each of these methods.
The model discussed here is specifically relevant to formal technology, encompassing design issues at every stage of development, but the notion of clearly delineating the return on investment for EDA solutions should be regarded as an essential part of the vendor / customer partnership proposition. Demonstrating not just the practical application of tools, but the dramatic impact they can have on time to market, risk and resources, shows customers you care as much about their business success, as you do about their design.