There’s a new kid in class.

We’ve all been through this scenario before.  All the players are comfortable in their established roles.  The leader tries to stay ahead and always communicates with the purpose of maintaining the perception of leadership.  The second player vies constantly with the leader for supremacy and mind-share, always trying to one-up the alpha dog.  The third through fifth players are constantly flanking, trying to differentiate and establish themselves based on supremacy in a particular niche.

For years now, Xilinx, Altera, Lattice, Actel, … Read More → "New Kid in Class"

Introduction

Over two-fifths of FPGA design projects fall behind schedule. In order to reduce risk of delay of product delivery, changes need to be made not just in verification and production but also in the design process. Design simplification must be a principle that starts at the beginning of the project life cycle – before verification of complex code has become the bottleneck that delays project delivery.

For FPGA design, there are several methodologies that can be adopted to make life easier for both design and verification engineers. Two of these … Read More → "Avoid FPGA Project Delays by Adopting Advanced Design Methodologies"

We always thought we knew how it would go down.

Under cover of darkness, our black-clad insertion team would rappel down the walls of the super-secret Xilinx fortress in the desert.  With the kind of precision timing and teamwork found only in movies and editorial feature introductions, we’d scan the perimeter and locate the vulnerable point.  A diamond-tipped drill bit driven by a silent motor would bore a hole just large enough for our fiber-optic viewing tool, and the telling video would be immediately beamed back to FPGA Journal headquarters.  At the … Read More → "Not Bad Die"

New process nodes have a predictable rhythm.  Until about 90nm, we knew before anybody announced anything that we’d get double the density, half the power (dynamic, of course), and 50% more speed than we had in the previous generation.  Of course, that made waiting for the announcements from semiconductor companies a little less than suspenseful.  Our Moore’s Law alarm clock would beep on its two-year cycle.  We’d check to see if anybody had announced the thing we were expecting yet, and then we’d hit the one-month snooze button … Read More → "40nm Altera Stratix IV"