feature article
Subscribe Now

Universities and Electronics

When the first semiconductors were created, they were the result of theoretical studies. As integration grew, so the device manufacturers and the equipment manufacturers pragmatically pushed ahead with brute force, scaling as they pushed down the Moore’s Law curve. Universities often struggled to keep abreast of developments, although, for a long way down the scaling curve, the mainstream underlying theories were pretty well understood.

Today we can no longer rely on scaling alone. Small channel effects, themselves difficult to understand and predict, are worked around by using double gates, raised sources and drains, surround gates, and vertical structures. These need objective evaluation and measurement. Techniques to cope with variability are starting from theoretical models as well as from pragmatism. At the same time, companies are moving from being fully integrated to “fab-lite” strategies and even selling off their fabs completely. To understand the requirements for manufacturing, the semiconductor companies and the foundries are turning to third parties, like universities, for help.

One example of a third party is IMEC, in Belgium, where production equipment manufacturers, chemical manufacturers, chip companies, and academics work with the research staff of IMEC to look at future technologies and work out the kinks before they transfer to front-line production.

The change in balance was evident at the UK’s National Microelectronics Institute’s forum on silicon variability earlier this year in London (http://www.icjournal.com/articles/2009/20090707_taming.htm). The keynote was given by Intel Fellow Kelin Kuhn. While, in her tour de force of a presentation, she referred frequently to practical results from Intel, she acknowledged that a chunk of her presentation was based on theoretical work carried out by Asen Asenov of the University of Glasgow.

The new Nanofabrication Centre at Southampton is a part of this trend for universities to take a more important part in theoretical understanding of technology. After the old fab, one that had developed over time and was CMOS based, burned down four years ago, the team working on the new building have had the luxury of a clean sheet of paper and some fairly significant funding. This has allowed them to make a series of decisions, which, while tough, would be the envy of many people in industry.

They moved to nanotechnology as the basis of the approach, both because solving the issues at nanotechnology levels will prepare the ground for further scaling and because it also allows cross-disciplinary research. A project that is already well advanced is the “Lab on a Chip.” Using silicon processed with NEMS (Nano Electro-Mechanical Systems) technology, routine chores, like blood cell counts, can be carried out immediately, rather than waiting for days for the results to come from a specialist lab.

The planning team also made a decision to spend up to 10% of the equipment budget on “risky” technology. One massive expense was a Zeiss helium ion microscope: one of only a handful in the world, in Southampton it has, even in the few months that it has been installed, moved from “risky” to “priceless.” It uses a stream of helium ions from a 3-atom pyramid at the end of a needle to combine microscopy with processing. Unlike a Scanning Electron Microscope (SEM), samples do not need a conductive coating. This saves time and money but, more importantly, gives incredible improvement in images – a nano-particle in a liver sample was wonderfully clear, but, as a side effect, it also showed researchers that liver has pores down to 30nm.

The ion beam can also be used for fabrication. With a potential 0.25nm resolution, it can mill materials like graphene to create grids with a 5nm pitch. It can create a 5nm dot pattern with a 14nm pitch in a resist without any proximity effects.

The facilities are being used by the university and by researchers from other universities, and there are already projects in progress with industry. So, at the top end, Southampton is today at the front edge, although, around the world, other facilities are chasing hard. But universities are not just research centres, they are also the primary source of engineering staff. One of the perennial debates between the electronics industry and academe is, “What can industry expect a graduate in electronics to know?” The argument is an extension of the old learning versus training debate. Industry, at least some of it, wants a graduate who is instantly employable on beneficial work. The universities see their task as carrying out the base work in providing the skills that will equip a student for a professional lifetime.

Now this raises a very interesting question – just what skills do electronics students need to have? Should graduates be able to solder? Should they be able to write a program? And in what language? Is Java appropriate? Should they be able to design a circuit using an HDL? (And which one?) If HDLs are just a passing technology to be replaced by ESL tools, is it worth teaching HDL use? In fact, should students be taught chip design at all?  Most of them won’t be joining the decreasing number of teams that are creating SoCs and ASICs. But aren’t FPGAs, which are being designed in staggeringly large numbers, going to require the same skills? The list is endless and also includes non-technical skills. Should graduates be able to write a report? Give a short presentation? Work in teams?

Southampton, again not uniquely, is regularly reviewing how it teaches, both internally and in consultation with industry. For a long time, the electronics students have designed small circuits in their second year. These are manufactured through CMP (Circuits Multi Projets) in Grenoble on multi-project wafers. However valuable this exercise may be, it does not reflect how real designs are undertaken. To provide a more realistic environment, Southampton is creating a brand new IC design laboratory. This has been made possible by a Charles Babbage Grant from Synopsys, the first such grant in Europe, and it gives the university licenses of Synopsys’s EDA software and intellectual property. Along with the tools, Synopsys will be providing support and faculty training. (Previous grant recipients in the USA include Case Western Reserve University, Purdue University, and Syracuse University.)

The exact way in which this will be integrated into teaching is still evolving, but Professor Mark Zwolinski of Southampton speculates that one approach may be to create a platform SoC for which teams of students will create new elements. This provides hands-on use of the tools to create a manageable block of design and then experience the integration and verification of a full-sized device.

Back to basics. Universities are providing the workforce of tomorrow. What should they be doing to prepare them? There are clearly certain basics that one can expect: understanding of circuits, logic, etc. But beyond that, the universities should be making sure that the specific tools that are used for teaching — the programming language, the design methodologies, etc. — are example tools that are best suited, at a particular point in time, to encapsulating the skills and knowledge that is being imparted. Graduates should emerge with open minds on choosing the best and most appropriate ways of working if they are to contribute, not just today, but in twenty and thirty years’ time.


Leave a Reply

featured blogs
Jun 9, 2024
I've seen several do-it-yourself (DIY) miniature versions of the Las Vegas Sphere, but this is the best contender thus far....

featured chalk talk

ROHM's 4th Generation SiC MOSFET
In this episode of Chalk Talk, Amelia Dalton and Ming Su from ROHM Semiconductor explore the benefits of the ROHM’s 4th generation of silicon carbide MOSFET. They investigate the switching performance, capacitance improvement, and ease of use of this new silicon carbide MOSFET family.
Jun 26, 2023