feature article archive
Subscribe Now

New Kid in Class

There’s a new kid in class.

We’ve all been through this scenario before.  All the players are comfortable in their established roles.  The leader tries to stay ahead and always communicates with the purpose of maintaining the perception of leadership.  The second player vies constantly with the leader for supremacy and mind-share, always trying to one-up the alpha dog.  The third through fifth players are constantly flanking, trying to differentiate and establish themselves based on supremacy in a particular niche.

For years now, Xilinx, Altera, Lattice, Actel, … Read More → "New Kid in Class"

Trans-Acting Lessons

It is not a notable occurrence for me to find myself confused at any given moment on any given topic. However, finding that I’m not the only one confused – well, that pretty much makes it a red-letter day. Within the world of SoC verification, there are numerous points of potential confusion, and I’m finding much satisfying solidarity with other folks trying to navigate the space.

Part of the problem arises from terminology and semantics. For succinctness’ sake, terms are given very specific meanings. The cognoscenti use such … Read More → "Trans-Acting Lessons"

Avoid FPGA Project Delays by Adopting Advanced Design Methodologies

Introduction

Over two-fifths of FPGA design projects fall behind schedule. In order to reduce risk of delay of product delivery, changes need to be made not just in verification and production but also in the design process. Design simplification must be a principle that starts at the beginning of the project life cycle – before verification of complex code has become the bottleneck that delays project delivery.

For FPGA design, there are several methodologies that can be adopted to make life easier for both design and verification engineers. Two of these … Read More → "Avoid FPGA Project Delays by Adopting Advanced Design Methodologies"

Not Bad Die

We always thought we knew how it would go down.

Under cover of darkness, our black-clad insertion team would rappel down the walls of the super-secret Xilinx fortress in the desert.  With the kind of precision timing and teamwork found only in movies and editorial feature introductions, we’d scan the perimeter and locate the vulnerable point.  A diamond-tipped drill bit driven by a silent motor would bore a hole just large enough for our fiber-optic viewing tool, and the telling video would be immediately beamed back to FPGA Journal headquarters.  At the … Read More → "Not Bad Die"

Shared Responsibility

Let’s face it: multi-threading has created some pains in the… well, as Forrest would say, butt-tox. You used to be able to write code assuming you had your own nice little sandbox, especially in a more protective language like Java, which allows you to be reasonably sure that some other schmo’s pointer won’t come weaseling its way onto your turf. But now you can have multiple threads that may want to get to the same pieces of data, so the threads have to learn how to play nice together, and … Read More → "Shared Responsibility"

Ten- Step Program

Power has become a key design consideration for SoCs in pretty much any application. We’ve looked at some ways of reducing power in past articles, largely at a high level. We continue here with a specific look at some techniques that can be identified by a new tool from Sequence called PowerArtist. This tool takes ten specific steps to identify ways to reduce power, although only a couple of them are automatically implemented. Most of them may take some engineering evaluation to decide whether to implement, and, if so, exactly how to do them, so those techniques … Read More → "Ten- Step Program"

40nm Altera Stratix IV

New process nodes have a predictable rhythm.  Until about 90nm, we knew before anybody announced anything that we’d get double the density, half the power (dynamic, of course), and 50% more speed than we had in the previous generation.  Of course, that made waiting for the announcements from semiconductor companies a little less than suspenseful.  Our Moore’s Law alarm clock would beep on its two-year cycle.  We’d check to see if anybody had announced the thing we were expecting yet, and then we’d hit the one-month snooze button … Read More → "40nm Altera Stratix IV"

Special Recognition

“OK people, can I have your attention please? I need you all to listen up. All right. Quiet… Now… I want you all to get in a line along that wall there. We’re going to be doing some recognition stuff this morning, so get in line and we’ll get you trained up on what you need to look for. We may not need all of you, but I need you here just in case. And if we need more than you guys, we may have to add another group of … Read More → "Special Recognition"

Three Chords and the Truth

Twelve Bar Blues is structured improvisation.  A standard twelve-measure chord progression repeats tirelessly, and the experienced blues musician lays his soul over this monotonous harmonic structure like a fine linen drapery.  Aart de Geus, President, CEO, and Co-Founder of Synopsys, the world’s second largest electronic design automation (EDA) company, is also an accomplished blues guitarist.

Blues in C
I (C) Measures 1-4:

The tonic orients the ear, providing a firm foundation of reference.  In traditional blues, it is repeated for the first four bars of the sequence, setting up “home base” … Read More → "Three Chords and the Truth"

High-Speed Serial Comes to the Analog/Digital Divide

Everyone knows that if you want to do things slowly, you do them one at a time. If you want to get more done, you get more people to help do things in parallel. Right? I mean, in the world of electronics, think “serial,” and what might come to mind is the slow, stately procession of bits plodding from your desktop to some not-very-needy peripheral. You want speed? Check out the parallel port, where multiple lines are willing and able to deliver the kind of data demanded by your more high-maintenance attention-craving peripherals.

Read More → "High-Speed Serial Comes to the Analog/Digital Divide"

featured blogs
Mar 28, 2024
The difference between Olympic glory and missing out on the podium is often measured in mere fractions of a second, highlighting the pivotal role of timing in sports. But what's the chronometric secret to those photo finishes and record-breaking feats? In this comprehens...
Mar 26, 2024
Learn how GPU acceleration impacts digital chip design implementation, expanding beyond chip simulation to fulfill compute demands of the RTL-to-GDSII process.The post Can GPUs Accelerate Digital Design Implementation? appeared first on Chip Design....
Mar 21, 2024
The awesome thing about these machines is that you are limited only by your imagination, and I've got a GREAT imagination....