Articles – Page 514

January 6, 2009

With increasing size and complexity of ICs and limitations in traditional physical failure analysis tools, failure analysis engineers need help determining the root cause of a specific failing die. Yield engineers, on the other hand, need to be able to identify systematic yield limiters that may be disguised as random failures caused by complex interactions between the manufacturing process and specific design patterns. A failure diagnosis tool that provides high accuracy and resolution, as well as meaningful defect classifications, can be of high value to both engineers’ jobs.Today, most complex ICs are tested using built-in scan test … Read More → "Layout-Aware Diagnosis of IC Failures"

And That Makes 1

A Look Back at 2008

by Bryon Moyer

January 6, 2009

A look outside confirms it. The sky ranges from dull white to steely dark gray. An occasional glimpse of blue is quickly corrected to bring it into conformance with the surrounding severity. The sound of the traffic is enhanced by the swish of tire on wet road. And it’s cold. By California standards, anyway… Yup, it’s winter. No, you don’t see this in the travel guides, but as the old year gives way to the new, Silicon Valley receives – hopefully – its annual drink of water from the skies, and would-be … Read More → "And That Makes 1"

Keeping Power Under Control

A Brief Look at PMbus

by Bryon Moyer

December 16, 2008

Nothing should be simpler than turning the power on and off. It’s just a switch. Switch it on; switch it off. Easy peasey. Right?

Well, not so fast. There ain’t just one power supply on a board anymore. These days you’ve gotta have in place a veritable cornucopia of power levels to satisfy all the finicky chips that are spreading like a bad mold across your boards. And the different power lines have different capacitances and different drivers, so that simply shutting the power down can conjure up images of leaves … Read More → "Keeping Power Under Control"

Power Considerations In FPGA Design

by Jim Turley

December 16, 2008

It is clear that systems operators regard power as a significant operating expense. These constraints trickle down to system designs and the boards that comprise those systems. In addition to operational costs, design complexity increases when dealing with thermal issues caused by excessive power. Port density and bandwidth requirements go up from … Read More → "Power Considerations In FPGA Design"

Verayo Leaves Tiny Fingerprints on Chips

by Jim Turley

December 16, 2008

How do penguins tell each other apart? For that matter, how to barnacles, or pigeons, or orangutans recognize each other (we know how dogs do it)? To our eyes, they all look pretty much the same.

The same could be said of FPGAs. Mass production is one of the hallmarks of the semiconductor industry, as identical chips stream off the production lines. Intel’s enormously successful manufacturing prowess revolves around the mantra, “copy exact.” Every Intel fab is just like every other Intel fab, and every chip is identical to every other chip. That& … Read More → "Verayo Leaves Tiny Fingerprints on Chips"

Starting From Scratch

A Brief Look at the Hidden World of TCAD

by Bryon Moyer

December 16, 2008

“You’re ready for tape-out already??”

“Yup!”

“Um… “ “And it meets all specs? In all corners and modes?”

“It should.”

“What do you mean, it should?”

“Well, we designed it to where it should. Of course, once we get silicon out, we can try it out and see if it all works. If not, well, we’ll make some tweaks and try … Read More → "Starting From Scratch"

Disziplin Muß Sein*

A Look at Recent Software Development Process Tool Announcements

by Bryon Moyer

December 9, 2008

Software development processes can vary dramatically. If you program only occasionally as a hobby, like me, then you dream up what you want to do and immediately start coding. Working units then randomly materialize and just as quickly disappear like quantum fluctuations. Moving into the more professional arena, if there is a process, it can vary from something light, agile, and extreme, where code is generated quickly and converges towards requirements using Brownian successive approximation, all the way to heavyweight rational processes with which you risk spending your entire career just reading the manual (understanding it would take even … Read More → "Disziplin Muß Sein*"

Low Cost Reconfigurable Computing Cluster Brings Millions of Reconfigurable FPGA Gates to Students

by Dick Selwood

December 9, 2008

Building on commodity hardware and industry standard software programming methods, Baylor group architects a $10,000 reconfigurable computing cluster.

Accelerated computing – using programmable logic and other non-traditional processing resources to augment clusters – has become increasingly popular. Most recently, the NSF announced that $20,000,000 in funding is available for research groups to push beyond petascale computing. Accelerated computing represents the leading edge of the high performance computing wave, as evidenced by the world’s fastest supercomputer, the Roadrunner cluster located at Los Alamos National Labs. Roadrunner makes use of commodity processors coupled with … Read More → "Low Cost Reconfigurable Computing Cluster Brings Millions of Reconfigurable FPGA Gates to Students"

IP for Complex FPGAs

by Dick Selwood

December 9, 2008

According to Gartner’s Jim Tulley, there are around 7,000 ASIC design starts a year, a number that is in slow decline. By way of contrast, there are around 100,000 FPGA design starts a year, of which 30,000 include a microprocessor of some kind. Yet for eleven years at the IP conference in Grenoble, the leading get-together for IP suppliers and users, the only mention of FPGAs has been in the context of building blocks for ASIC prototyping tools or, more recently, for testing the market before undertaking the incredibly more costly task of building an ASIC.

Obviously, … Read More → "IP for Complex FPGAs"

Uncanny Resemblances

Synopsys Announces Base Curve Compaction for CCS Models

by Bryon Moyer

December 9, 2008

If you had all the time in the world, you could simulate an entire SoC using SPICE, but you don’t, so you can’t. At least not for digital circuits; analog is different, since detailed analysis is required there, and it’s not a billion transistors. And yet, even with digital, we can’t quite revert all the way to 1s and 0s, but we can start to use some abstraction in the form of library cells for basic circuit chunks like transistors, inverters, gates, and flip-flops. Those cells can be characterized using SPICE ( … Read More → "Uncanny Resemblances"