feature article archive
Subscribe Now

Getting Around Limits By Getting High

If you were able to record the development of a town as it grew into a city over years and decades and then speed up the film in a super-fast-mo replay, you’d notice, assuming you weren’t thrown into an epileptic seizure by the rapid day/night flashing, that things start in a small center and move out for a while. Farmlands are replaced by tract homes, forests are cut down, hills may be leveled or developed, and the town inexorably creeps outward like mold in a Petri dish.

At some point, a limit … Read More → "Getting Around Limits By Getting High"

Toys for Engineers in Automotive

There is an old story about two shoe sales people sent to a desert island. The first looks around and sends a message back to head office, “No one here wears shoes. Coming home on next ship.” The second sent a message to his head office, “No one here wears shoes. Send several hundred pairs on next ship.” The mood at the Paris International Automotive Electronics Congress (IAEC), earlier this month, was more like that of salesman two. The tribulations of the mainstream auto market, particularly the US, was recognised, but the view was that … Read More → "Toys for Engineers in Automotive"

Minimizing the Pain of RTL Design Reviews

Design reviews conger images of engineers carrying reams of code printouts, filing single-file and head down into a room to be judged by others. The positive impact of design reviews has been proven though many studies, but does the preparation and process of the review have to be so painful? This paper provides a practical approach to design reviews that soothes the process and actually results in a positive experience.

The key to a painless design review process is to use techniques and tools as code is developed that contribute to a quality solution, minimizing the time … Read More → "Minimizing the Pain of RTL Design Reviews"

HardCopy in Practice

Altera has carved a unique niche in the market with their HardCopy ASIC offering.  As we all know, FPGAs offer some compelling benefits when compared with traditional ASICs – short design cycles, zero-NRE, and in-field re-programmability are the ones most often cited.  For low- to medium-volume applications, FPGAs can be a wise choice compared with a high-risk, high-NRE, low-volume ASIC run.

FPGAs are not a panacea, however.  Low-cost FPGAs don’t have the speed, capacity, or rich feature set of their high-end brethren.  If you need advanced capabilities, you’ll pay an advanced price, … Read More → "HardCopy in Practice"

Entering the Spin Zone

Some time back we took a brief look at MRAM technology, mostly from the standpoint of contrasting it with FRAMs, triggered by a specific paper regarding an MRAM-based flip-flop. That was a somewhat unusual implementation of the MRAM concept that happened to provide a quick technology contrast but didn’t really get to the heart of what’s going on with MRAMs. So we’re going to dive deeper here in the hopes that spin technology ends up meaning more than technology that causes my head to … Read More → "Entering the Spin Zone"

Hooking Up

The number of options for getting from point A to point B keeps growing. It’s one of those areas where the concept of “standard” is somewhat loose, since there are so many of them you might wonder if the word even applies. Connectivity in larger embedded systems historically took advantage of backplane standards that allowed different cards to communicate with each other; smaller form factor devices often didn’t need the kind of data transfer rates that would warrant a complex protocol.

As miniaturization has shrunk erstwhile cabinets into our palms, the … Read More → "Hooking Up"

Take as Much Time as You Need

Those of you familiar with San Francisco may have traveled a beautiful seaside stretch of road called the Great Highway, which runs from Ocean Beach down to the zoo. The portion south of Golden Gate Park is less traveled and passes through sparsely vegetated dunes with no intersecting roads. However, even though the road is isolated from the Sunset District’s vehicular traffic, the beach is made accessible to local pedestrians via a series of crosswalks protected by stoplights.

Coursing down this way at 2 in the morning, you’ve got a good chance of being … Read More → "Take as Much Time as You Need"

Who’s Winning?

Let’s face it, we’re a competitive species.  People like to compete in just about everything they do.  We’re not psychologists, so we can’t speculate with much authority on the Ids and Egos that drive our drives to win, but we can certainly see the results – in everything from our obsession with sports to our capitalist system of business.

An important by-product of our competitive nature is our attention to score keeping.  We constantly strive to establish metrics by which we measure our progress and success & … Read More → "Who’s Winning?"

Rooting Out Software Heresy

For those of you who don’t regularly visit the comments at http://www.journalforums.com/ (and you should), my piece two weeks ago on “Taming C?” generated a number of comments. These got me thinking. The outcome of these thoughts seemed sufficiently relevant to all regular readers of ETJ that it was worth writing a full-length article rather than just posting replies.

The article started, “There is a problem with the C programming language.” It went on to argue that … Read More → "Rooting Out Software Heresy"

Battered and Bedraggled

These are interesting times at Cadence. A bit too interesting. If you read some of the press blips over the last few weeks, it’s over; investors have given up; time to fold the tent and go home.

Wha? How could a solid EDA denizen find itself in such a position? And is it really over? Or is the press exaggerating? (Although really, since when does the press exaggerate?)

OK, granted, the stock price is at around 1994 levels (adjusted for splits). I’m not one to follow the financials as much as the … Read More → "Battered and Bedraggled"

featured blogs
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...
Apr 18, 2024
See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.The post Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud appeared first on Chip Design....
Apr 18, 2024
Analog Behavioral Modeling involves creating models that mimic a desired external circuit behavior at a block level rather than simply reproducing individual transistor characteristics. One of the significant benefits of using models is that they reduce the simulation time. V...