Let’s start with some thundering generalisations. It is taking too long to bring SoCs to the market. A big bottleneck, and a large and growing part of the overall cost of an SoC, is developing the software to run on the embedded processors. It is often not possible to begin software development until the chip architecture has been pinned down, which severely limits the influence that the software team can have over the architecture. The desk-top development environment, in which software is usually developed, behaves differently to the target environment. Hardware prototypes in, for example, FPGAs, if … Read More → "Open, Virtual and a Platform"

Parasites are generally not perceived as a good thing. They benefit at the expense of something else. There’s none of the quid pro quo associated with a symbiotic relationship. There’s a clear winner and a clear loser. The question is whether or not the host can muster the wherewithal to withstand the parasite, even if the hanger-on can’t be shaken off completely.

Semiconductor ICs suffer from parasites. They’re the uninvited capacitors and resistors and their ilk that attach themselves to brilliantly conceived circuits, typically challenging the mettle of the … Read More → "Hijacking the Hijacker"

As you approach the entrance, you know you’re in the right place. You almost feel it before you hear it. A few more steps and there remains no doubt. The unmistakable thump of some serious bass brings with it the promise of some serious hip-hop.

This club is much like any of a number of similar clubs you can find anywhere in any major metropolis. As with any musical event, the evening starts with the little-known people, the upstarts, those that feel they have something to say and need to prove that what they have … Read More → "Guarding Against Interlopers"

With increasing size and complexity of ICs and limitations in traditional physical failure analysis tools, failure analysis engineers need help determining the root cause of a specific failing die. Yield engineers, on the other hand, need to be able to identify systematic yield limiters that may be disguised as random failures caused by complex interactions between the manufacturing process and specific design patterns. A failure diagnosis tool that provides high accuracy and resolution, as well as meaningful defect classifications, can be of high value to both engineers’ jobs.Today, most complex ICs are tested using built-in scan test … Read More → "Layout-Aware Diagnosis of IC Failures"