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Remote Possibilities

The truth is, our fifth-grader has become the equivalent of a live-in Support Desk. True, my husband and I are the designers of the entertainment system. We did all the research and navigated the DLP, plasma, HDTV decision process. We determined the optimal configuration for the accompanying sound system, exercising liberal design reuse (read: we kept our old stereo equipment). But our kid is the one who has really taken the time to make everything sing. He challenges the performance potential of the system and identifies bugs (he’s the one who figured out the work-around for our & … Read More → "Remote Possibilities"

Altera Looks Forward

In the rough-and-tumble, day-to-day, my-chip’s-bigger-than-your-chip schoolyard scrap that characterizes the top tier of the FPGA industry, a glimpse of vision, long-term insight and strategy are a rare breath of fresh air. We often feel that the two toughest competitors in the business spend too much time staring each other down and not enough time strategizing on how to conquer more of the vast landscape of logic design opportunity waiting patiently at the forefronts of their fiefdoms. However, when we sat down this week with Danny Biran, Altera’s Vice President of Product and Corporate Marketing, vision … Read More → "Altera Looks Forward"

Bundling Performance

Every year, FPGA and Structured ASIC Journal has conducted a survey of design teams that have recently completed projects using FPGAs. We collect and analyze a large volume of responses from readers regarding their completed projects, and we publish and sell a detailed report to companies that have a vested interest in gathering data about the current behaviors of FPGA design teams. This is nothing unusual, as many media companies perform similar research and offer similar studies to their customers. This time, however, we noticed one thing that was unusual. There seems to be a shift that … Read More → "Bundling Performance"

Tyranny Take Two

If all of this is seems a bit confusing, you might want to re-read part one of this series – “Tyranny of the Metaphor,” (read) where we discussed the problems with planning software projects using conventional methods like PERT charts and Gantt diagrams. This time, however, we’re going to roll up our sleeves and start solving the problem one piece at a time. As with almost any good therapy, we need to look deep inside ourselves first. As a group, … Read More → "Tyranny Take Two"

Just What is Algorithmic Synthesis?

In a traditional FPGA design flow, crafting the hardware architecture and writing VHDL or Verilog for RTL synthesis requires considerable effort. The code must follow a synthesis standard, meet timing, implement the interface specification, and function correctly. Given enough time, a design team is capable of meeting all these constraints. However, time is one thing that is always in short supply. Deadlines imposed by time to market pressures often force designers to compromise, resulting in them to settle for ‘good enough’ by re-using blocks and IP that are over designed for their application.

In the … Read More → "Just What is Algorithmic Synthesis?"

More and Moore

Price, Performance, and Power – the three Ps of Moore’s Law — have fueled four decades of technological fury. Each new process node brought us more gates per square meter of silicon, reducing price. Each shrink of the gate also brought us faster toggle rates, giving higher performance, and each narrowing also gave us the opportunity to operate at lower supply voltages, giving less dynamic power consumption. It seemed as if everything would improve exponentially forever.

Of course, nothing is free. There has always been another exponential curve at work as well – that … Read More → "More and Moore"

Need More Performance?

Extracting higher performance from today’s FPGA-based systems involves much more than just cranking up the clock rate. Typically, one must achieve a delicate balance between a complex set of performance requirements – I/O bandwidth, fabric logic, memory bandwidth, DSP and/or embedded processing performance – and critical constraints such as power restrictions, signal integrity and cost budgets. Moore’s Law notwithstanding, to maximize performance while maintaining this balance, the FPGA designer must look beyond the clock frequency altogether.

Overcoming Performance Bottlenecks

Each new generation of process technology brings with … Read More → "Need More Performance?"

Looking Inside

As FPGAs grow faster and more powerful, our natural inclination is to scrape more and more functionality off our boards and cram it into our new, bigger FPGAs. It’s a strategy that makes good sense. Not only do we save board real estate, increase reliability, and cut bill of materials (BOM) cost, but we also usually improve our performance and, paradoxically, reduce our FPGA’s I/O requirements. In addition, we put more of our circuit into the “soft” arena, allowing future upgrades, patches, and variants to be made with only an FPGA bitstream … Read More → "Looking Inside"

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