Kevin Morris (Editor, FPGA Journal): We did an interview two years ago when you first started as CEO of Xilinx. How have the first 2 years gone?
Moshe Gavrielov (President and CEO, Xilinx): It’s been a blast. I joined because I felt that everything was going toward programmables, and that feeling has just been reinforced the past 2 years. Now, I believe we have reached a threshold where it is going to accelerate. Of course, I’m sure you have heard this from many frothy FPGA CEOs over the years before, and the question is what’s different now? To be perfectly honest, I feel like the message of FPGAs was oversold. Primarily, there were other alternatives, and FPGAs were not quite there in a whole host of ways. What’s happening now is that the other alternatives are quickly disappearing. The demise of ASIC has been well documented, and there’s a lot of data to support that, but now a similar thing is happening with ASSPs.
As the semiconductor industry was maturing, there was a huge influx of money coming into the semiconductor world through government, venture capitalists (VCs), and the stock market. But, if you look at what has happened over the past 10 years, the return on those investments has been terrible, and therefore there is now much less money coming in. I think that trend is not going to reverse itself, because the VC world has gone through its own crisis. They have not seen positive return, so they’re actually seeing their partners [Limited Partners – LPs] investing a lot less. One critical thing that the LPs discovered during the last downturn is that, since you invest 10 years at a time and you are committed for a certain period of time, there is absolutely zero liquidity. Investors are now recognizing that liquidity is important. Not only could they not pull money out of a commitment, they still had to continue to fund. If you commit a certain amount of money and you’ve paid a portion, that money is still on call, and you end up sending more money in to protect your previous investment when you’d really rather be pulling money out.
With the poor returns, there is less and less money available, and, at the same time, semiconductor development costs are rising. The VCs are having difficulty, and lots of them are putting their money elsewhere. It’s not like there won’t be any more semiconductor startups, but the huge influx of cash is gone. The result is there will be fewer niche semiconductor startups with fully-optimized silicon that addresses the customers’ requirements. So, given that there will be fewer ASSPs and given that ASICs are prohibitively expensive, we’re [with FPGAs] actually at the point where at 40nm and the nodes beyond – you can do interesting things, hit interesting price points, and address the power concerns. The overhead of the programmability is shrinking on a marginal basis – moving rapidly and bravely and briskly into the world of the programmable imperative. There are a lot of things we need to put in place to make this happen. Despite what I’ve just said, it’s not going to fall like an over-ripe apple into our lap. If we don’t execute, it might fall on our head and make this squishy noise…
Kevin: So what you’re saying about the economics also sounds like market conditions should favor established companies that already know the ropes and have already established an infrastructure and a track record – compared with startups that are trying to get going from zero. Do you think the technology, with the marginal cost of programmability going down, is also favoring the FPGA as a more viable option?
Moshe: Absolutely. If I look at what we’re putting on the 40nm generation – and particularly if I look at what we’re doing with the next generation (which – without going into details — it’s faster, it’s cheaper, it’s higher SerDes, it’s more memory — and that implies that you can either hit higher functionality to compete with the high-end ASICs, or get lower cost to broaden and reach the higher volume applications. Now, it’s finally getting there. Again, I think programmability used to be over-sold. I was in the ASIC world and we usually thought it was a joke. 10-15 years ago we heard, “Look out, FPGAs are coming… they’re coming,” but what the FPGA industry was doing was over-hyped. We had system gates and other nebulous numbers that nobody understood…
Krishna Rangayasee (Vice President, Corporate Strategic Planning, Xilinx): Let me add to what Moshe just said. You could almost take the Gartner Hype Cycle – looking at the possibility of technology convergence – and apply it to FPGAs. First, there are a lot of hype and expectations around a new technology. Then, we go through a cycle of dissillusionment where people say, “Well, not really.” But then, we hit an economic tipping point where the technology becomes mutedly viable – it will hit certain market segments but not be generally useful. Today, [with FPGAs] we are at a tipping point. Moshe and I have been visiting customers – between the two of us maybe 200 customers within the past two years, and we’ve heard clear and consistent messages. What we’ve seen is that our customers are unable to sustain their pre-bubble-era R&D investment. They scaled R&D down to become profitable. That worked, and they are meaningfully profitable today, but they cannot afford to go back and start ASIC programs. These are 25-30-40 million dollar programs – one shot deals – and if you get it wrong, it can be a disaster.
Kevin: So, a lot of what Moshe is describing in the VC world happens on a different scale inside large companies?
Krishna: Exactly, and it’s a huge lobbying effort right now inside these companies because ASIC is a huge expense. These companies are struggling to figure out what other options they have. ASICs are becoming less and less viable. Since they reduced their R&D, somebody had to step in and fill the void and do the innovation. For the past 7-8 years, that was the ASSP companies, and that’s why they grew. But, as Moshe explained, the ASSP companies are now on question marks.
We are now being approached by a lot of our customers who are saying “OK, Xilinx, you are already my usual-suspect for design start. I use you for all my prototyping, but now I’m starting to use you in low-volume and mid-volume applications for production. Could I potentially do more things with you? And, how does the total cost of ownership work out?”
We are obviously not a fit for everything, but we are increasingly becoming a better fit for more things.
Kevin: Is there a trend of ASSP companies using FPGAs as their platform?
Moshe: I think particularly on the next process node you’ll see that becoming prevalent.
Krishna: It’s been talked about for many years. While the possibility was always there, and the economic model was working, we had not yet hit the tipping point of technology mix. But now, we have the critical elements – SerDes, power, performance, memory – the technology confluence of what an ASSP company would roll custom silicon for – they now have in an FPGA embodiment. The biggest delta is still cost, and I think with the next process generation – particularly in the low-cost FPGAs — it is becoming more possible. Then there is also the business proposition that needs to be worked out.
Kevin: You can obviously replace a lot of sockets where there was an ASIC in the past. In those situations there is already an engineering team that understands HDL-based design methodologies. But in a lot of the newer markets, there is still a designer and tool gap there…
Moshe: Yes, that’s what I was alluding to when I said we have to run very quickly, and it won’t fall into our laps. We are still serving a limited customer base because of designer expertise, and we have to broaden that customer base. That means making ways for people to work at higher levels of abstraction, making the tools easier to use, and making the out-of-box experience a lot more efffective and efficient than it has been. We have a great opportunity in front of us, but there is a lot that has to go into enabling that broadening on our side. The alternatives are becoming less and less attractive, and therefore we are bubbling up, but we need to push the technology to make it easier to use. We need to address the ecosystem more effectively.
Our strategy is one where we will continue to provide the tools for the implementation side – in particular as it’s tied in with the physical embodiment of design, but everything above that is an opportunity for EDA players. We need to make it easier for them to participate, plus the business model on their side needs adjusting in order for them to grasp that opportunity. The number of design starts EDA is servicing, particularly at the bleeding edge, is dropping precipitously. There is no natural trend for tens — let-alone hundreds — of semiconductor and system companies to move forward with ASIC at the latest node. The technology is not advancing more slowly, but there are fewer people that can do it and are willing to assume the risk. We [in the FPGA industry] have the opportunity to move in and fill that gap, and there is an opportunity for EDA to move in with more abstract tools. Traditionally, most of the EDA companies focused on selling tools to large semiconductor and system companies, so the transition to selling to FPGA customers and the change in the business model is very difficult. Their sales channels are a huge asset to them, but it’s hard to re-deploy that sales channel to satisfy these merging markets…
Kevin: Do you think EDA was burned in the past by FPGA and they are a little afraid to jump back in the water?
Moshe: I think it is too big an opportunity for them to skip. Anything else they do that requires them to branch away from where their core strengths are is riskier.
Kevin: So, you pointed out that in ASIC, EDA’s direction is to keep building more and more complex tools for a smaller and smaller audience. If you project those lines out into the future, that doesn’t seem like it ends in a great place.
Krishna: As we move down the line in the realm of fulfilling customer needs, we are bringing in the technology complexity issues that ASICs are facing today – 10Gb SerDes, power issues, predicting pin layouts a year before the design starts. So we’re bringing up the challenging problems that EDA companies are good at solving, but in an area with rapidly increasing design starts. I think that means there is enough opportunity for everybody to partner and drive towards growth.
Kevin: So, technologies like high level synthesis – which we’ve covered a lot, seem to be becoming viable as a way of managing some of this complexity that a typical design has going into it, and it seems like the advantages of a design tool technology like that are more realizable in FPGA than they are in ASIC. Because, in ASIC, if you cut down the architectural design of your system by 10x-20x, your total project is still almost the same size. It’s almost like applying Amdahl’s law to design cycles. But FPGA projects have much shorter verification cycles, so they stand to benefit a lot more from tools that can shorten the design phase. Is that an opportunity for EDA in FPGA?
Moshe: Yes, because the implementation cycle is so long on an ASIC that getting rid of the design cycle is a smaller part of the problem, but on an FPGA it’s the other way around. If you shorten the design cycle, you’ve saved a lot. By the way, that probably trivializes the verification on FPGA designs. But the flexibility and fast turnaround time on FPGAs enable you to take risks that you cannot afford to take on an ASIC. If you don’t have your ASIC 99.9% right, you’re in trouble, because you have these long expensive spins that will push you out of the market. With FPGA, you have these fast iterations that you can use to try new things and still manage the risk. The better we do in making those iterations faster, the more lopsided this FPGA innovation advantage becomes.
Kevin: So, does the decline of ASIC and the impact on the ASIC ecosystem come back around and bite you guys from the back, since those are the tools and technologies you need to deliver your next generation products?
Moshe: What we invest in each generation of technology becomes larger and larger, so we’ve had to become more judicious in how we invest our R&D budget, because we see that – we see it in spades – we see the challenges like cross-chip process variation – who want’s to deal with that nonsense? We deal with it because we can amortize the cost over a large market and a very broad set of applications, but a company that is designing an ASIC every other year – how can they afford to do that? Where do they get the skill sets?
Krishna: The amortization model works in our favor. We have a lot of IP we can re-use generation-to-generation. If we do our job right and expand the amortized customer base, it will always be easier for us than for the individual company doing occasional ASICs.
Kevin: Do you see another advantage in the decreasing marginal cost of IP in terms of resources? For example, looking at your recent announcement with ARM, the amount of an FPGA taken up by an ARM processor is becoming trivial, and the more stuff you can harden in an FPGA, the more areas you have equal footing on power, performance, and cost – competing with ASIC technology.
Moshe: That’s absolutely right – as more of the value of the system collapses into the FPGA, the more elements that can be pre-hardened for power, performance, size, and ease-of-use does make it beneficial to us. That’s a percentage of the design that no longer suffers from the FPGA tax of less-optimized silicon. The trick there is to find the balance of the right things to harden. If you get the right things in, you’re a hero. If you get the wrong things in, you’ve just added cost and complexity to all of your customers that they won’t benefit from. We have key customers that have shown us the amount of money they spend with Xilinx, and they have asked us why it’s always going up – and if that means we are charging more, but in reality so much of the value in their board is now moving into the FPGA – transcievers, buffers, fifos – all these used to be a large element of real-estate and cost, and now there’s a lot less of that on the board – it’s all moved into the FPGA.
Kevin: Has this changed the way you have to sell since you’re now more of a strategic partner instead of just a supplier?
Moshe: That definitely is a challenge. The market has changed, and as a result we have a lot more direct interaction with our key customers. We have a lot of very specialized people in the field to support this. It’s not easy because you need the people with the right skill sets at the right customer at the right time. Balancing all this is quite difficult.
Krishna: Obviously, since we have 19,000 customers, there is a tiering of where they are and what they do. In certain customers, since we are the heart of the system, we are very heavily partnered even at the concept level. They need us at the table because we are their technology partner. It’s a very different model than just talking to distribution and asking, “Should I buy a 32 IO part, or a 16 IO part?” It’s a very different ballgame with key customers having their entire systems centered around an FPGA. However, as we expand our customer base, and as more customers are taking advantage of programmability, we still have a very broad base of customers to support. That means our sales process is very nuanced – from direct customers to rep customers to distribution customers – we have to support them all very well.
Moshe: We see the VPs of engineering, the CTOs, and the general managers at all our key customers. When I was in EDA, we were often frustrated that we couldn’t always get those audiences. I think the difference is that, while EDA tools were in the path to the solution, they weren’t considered part of the solution, so we didn’t get the same level of respect.
Krishna: I’ve been at Xilinx over 10 years. Since our 40nm products are being discussed, we are seeing vastly increased interest from the very high-up management in our customers wanting increased visibility into our roadmap, our paths, and how they can partner with us to influence our decision making.
Moshe: …and this is very different from what I see with other semiconductor companies. I worked at LSI for close to 10 years, and at the time it was the premier ASIC company – at the center of Sun Workstations, SGI graphics, PlayStations, Cisco routers – and you’d get that visibility. If you were selling a high-value component, it was still a commodity, whereas custom logic is a differentiator that sits at the heart of the system. It’s very refreshing, and that’s one of the best parts of the job is to go and see what the customers are doing – and to partner with them.
Krishna: It’s very refreshing to see the amount of time our customers want to spend with us and the amazing things they’re doing with our products. It’s a very big change since I’ve been here.
Moshe: People take it for granted that the flexibility and value of FPGAs grows, since it was always part of the DNA. But since the value of FPGAs has grown so much over time, people are starting to take advantage of them in new ways – they are designing for upgradeability. They take the FPGA and only use a certain percentage of it because they know that in 6-12-18 months they are going to need to add new capability and they want to be ready.
Kevin: So they are now designing platforms and not just devices too?
Moshe: Exactly, and it’s interesting because, as we’ve done things like EasyPath to reduce cost, (customers think cost is a big issue and this is an easy way to achieve cost reduction), a surprising number are telling us they have to keep programmability because they are dealing with applications where it’s too expensive to replace hardware and they’re using flexible, upgradeable platorms to extend the life of their system.
Krishna: As hardware becomes a mechanism for you to deliver your IP, you’re looking for things that extend the shelf life because physical hardware development cost is very heavy. Customers want to stay in-market with feature upgrades, bug fixes, and reducing truck rolls. Many base station customers today use FPGAs that are field-upgradeable.
One of our wireline customers was just talking to me about how they need to reduce the number of suppliers they use. They have 17 different ASSP suppliers, 3 ASIC suppliers, and 4 MPU suppliers. They want to move it to just 2 or 3, and there are great economic benefits to what they want to achieve with that. And now it’s tangible to fit a lot of this functionality into FPGA and achieve a total cost-of-ownership reduction in doing so. So, what they’re looking at is a single FPGA with a standard set-up. Then adding IP and upgradeable connectivity interfaces and upgradeable personalities into the FPGA. So, they can deploy a platform with the FPGA and after the fact decide what personality it assumes, what connectivity it assumes. Do you want 1G bandwidth or 10G bandwidth? They don’t want to build separate boxes anymore. Cost of ownership becomes a very big issue that tends to favor the FPGA solution.
Another one of our customers told me “I cannot get 10G SerDes technology even if I paid all the money I had. I’m not at the right volume point.” As we cross 40nm and as we go to the next-generation node, the technology that FPGAs will be offering will be on-par or even ahead of the ASICs – and you can buy in volumes as low as one chip. 10 gig is 10 gig. There is now hardly any technology that is available that FPGAs don’t have at the cutting edge. We are leading with process, we are leading with SerDes, and as we keep knocking on cost and power, we continue to gain ground – and we bring all that advantage to 19,000 customers. Our key customers are really smart and are recognizing the trends. They are now very concerned about their supply chain. They’re worried about the cost of ASICs and they’re worried about who is going to supply their ASSP. Obviously we have to close gaps on tools, productivity, cost, and power to win that business.
Kevin: We’ve talked a lot about FPGAs competing with other solutions in the market. How does Xilinx defend itself within the FPGA market itself with patents expiring and more competitors emerging?
Moshe: Well, first it’s incumbent on us to run very fast. It’s a big investment to compete in FPGA. We have R&D approaching $400M/yr, which is a big number, and then the other element is the channels and technical support. We have to keep moving all that forward as quickly as we can. If you look at what’s happened in the FPGA space, a number of people have come and gone and it’s still Xilinx and Altera fighting for most of the FPGA market at this point in time. There is always the expectation that a big semiconductor company might enter the market, but in reality, the FPGA business is a service business. We’re projecting a very complex technology to a lot of customers, and if you think about typical excellent semiconductor companies, they don’t think that way – they’re not primarily in the service business. It’s a retail versus wholesale mentality, and the customers, for a large number of applications we’re in, really are in the retail market and not the wholesale market. With the investment in R&D, the channels we have, and the complexity of the product, those are pretty good defenses to have, but we need to continuously keep running. If we slow or stop for two or three years, a lot of this withers – and there is something interesting and challenging in that. If you compare it to nearly any other space in the semiconductor world, it is a challenging and difficult business to be in because it’s multi-disciplinary. You have to give them silicon, IP, software, then take them through the system and figure out how to implement their ideas and map them onto your solution. Krishna’s most popular quote is, “It’s the platform for innovation for tens of thousands of new designs per year from Mars to Antarctica.” – That sounds bombastic, but it’s actually what we do. Who else does that?
Photo of Moshe Gavrielov by Laura Domela
One thought on “A Mighty Wind of Programmability”
Quote”Kevin: You can obviously replace a lot of sockets where there was an ASIC in the past. In those situations there is already an engineering team that understands HDL-based design methodologies. But in a lot of the newer markets, there is still a designer and tool gap there…”
And the EDA industry is still focused on synthesis and ignoring logic design.
I am a logic designer that is continually annoyed that the so called “tool chain” is unsuited for design entry.
And Xilinx continues down the same old path. Designers were forced to use HDL because management was so focused on the need for simulation that designers were brainwashed into using HDL for design entry.
HDLs are such a poor fit for design entry that it is sickening. Spreadsheets and FSMs, humbug. Boolean and Arithmetic Expression Evaluation is key.
Design entry is essentially data flow programming and there is nothing about EDA that focuses on that.
Yes design is hard — because EDA vendors focus on synthesis and Xilinx is doing the same thing. Meanwhile Intel is pushing one API — I forgot the correct name.