Stacked Silicon Interconnect Technology Implemented in ISE Design Suite
This video features stacked silicon interconnect technology and how it is implemented in the ISE design suite. Liam Madden, VP of Silicon Technology explains…
This video features stacked silicon interconnect technology and how it is implemented in the ISE design suite. Liam Madden, VP of Silicon Technology explains…
If you are a member of an SOC design team, or if you manage one, then memory is critically important to you. On today’s multicore SOC designs, more on-chip silicon is devoted to memory than to anything else on the chip and yet memory is often added as an afterthought. Don’t let that happen to your team.
This white paper discusses the many alternatives for on-chip and off-chip memory usage … Read More → "Everything You Wanted to Know About SOC Memory*"
Nearly all new ASIC and SOC designs incorporating digital audio employ some form of programmable DSP to run the audio codecs. General-purpose control processors can implement audio codecs with a sufficiently fast clock. However, they are not the most efficient engines for running audio codecs, and almost always use more energy to deliver real-time, multi-channel audio.
DSPs generally run audio codecs more efficiently than do general-purpose processors because they have features that accelerate the … Read More → "Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC"
DSP software developers have traditionally converted key performance-critical portions of their algorithms to assembly language because that was considered the only way to achieve high performance when using a DSP core. Every DSP architecture is different – optimized for a different type of data throughput challenge – and programmers need to understand each underlying DSP architecture in order to optimize the code manually using assembly coding techniques. Thus specialized knowledge is required to achieve effective results.
Read More → "Cut DSP Development Time – Get High Performance From C, No Assembly Required"
The choice of hardware-interconnection mechanisms among processor blocks in an SOC affects communication performance and silicon cost. The default on-chip communications choice for most ASIC and SOC design teams is the global bus or a bus hierarchy, however this choice automatically incurs many performance and design problems.
There are other choices that may be more appropriate for today’s nanometer ASIC and SOC designs. These choices match well with communications concepts frequently used by … Read More → "Get Your ASICs and SoCs Off the Bus!"
Texas Instruments continues to expand the performance of its processors with the new C6A816x Integra™ DSP+ARM processor generation, featuring the highest performing floating- and fixed-point digital signal processor (DSP) on the market today.
Emulation: The Enabler for Hardware-Software Co-Verification
Using an emulator for ASIC verification holds the promise of extremely high execution speed, enabling the validation of system-level scenarios that are unthinkable with simulation farms. With MHz speeds, today’s fast emulators can crunch enough cycles to run entire software application stacks on top of an SOC and truly perform hardware software co-verification. However, having a fast and accurate model of the ASIC solves only half of the problem. … Read More → "Next Generation System Validation Using Transactors"
Lower power consumption and higher bandwidth are now the two dominant requirements in designing next-generation high-end applications. The global trend across multiple markets is for higher bandwidth in the same footprint at the same or lower power and cost. The Internet is going mobile and video is driving bandwidth requirements at a growth rate of 50% year on year. The march to 40G and 100G systems (with 400G on the horizon) is underway to support this ever-growing bandwidth demand. Fierce competition is driving down prices. Space constraints abound, and … Read More → "Reducing Power Consumption and Increasing Bandwidth on 28nm FPGAs"
Explore a new a new paradigm for industrial control using a standard ARM-based processor architecture to create a unified control environment.
Texas Instruments’ (TI) Integra™ DSP+ARM devices combine a digital signal processor (DSP) and an ARM® processor, enabling developers to create applications best suited for executing a combination of signal processing tasks and microprocessor (MPU) tasks. This paper reviews the benefits of combining ARM processing with DSP processing in a single chip, including increased real-time performance, improved system flexibility and reduced system cost and power. Integra DSP+ARM processors are useful for applications such as power protection systems, industrial control, machine vision and … Read More → "Maximizing the Power of ARM with DSP"