The advantages of using programmable logic to get electronic products to market quickly with less risk and cost are well known and recent market drivers have shifted even further in their favor; new economic realities coupled with changing consumer behavior, shorter product life cycles, richer feature sets, and faster upgrades, to name a few. In step with these demands, high-end FPGAs are now architected using geometries down to 40nm and with capacities of up to five million equivalent ASIC gates. They include performance optimized I/O’s and dedicated DSP … Read More → "Beyond Physical: Solving High-end FPGA Design Challenges"

In a typical FPGA design flow, most designers work from a written specification that contains architectural level drawings defining the major logic blocks, interfaces, and busses. The design manager begins to partition functionality based on the diagrams and to assign development based on the block’s functional descriptions. Each block is coded individually and may be simulated in a block-specific test bench. The team assembles the blocks into a device-level file where the ports are pins on the target device. The design is then ready to be compiled for simulation initiating the … Read More → "Fast, Efficient RTL Debug for Programmable Logic Designs"

As field-programmable gate arrays (FPGAs) have grown in capacity, complexity and performance, their associated design and verification tools, infrastructures and methodologies have struggled to keep up. Today’s FPGAs may contain the equivalent of millions of logic gates and run hundreds of thousands of lines of embedded software. Such designs may involve multiple hardware design teams, software development teams and verification teams located around the globe. In order to address designs of this size and complexity it is necessary to employ what is known as hierarchical team-based design.</ … Read More → "The Great Divide: Why Next-Generation FPGA Designs will be Hierarchical and Team-Based"