In a typical FPGA design flow, most designers work from a written specification that contains architectural level drawings defining the major logic blocks, interfaces, and busses. The design manager begins to partition functionality based on the diagrams and to assign development based on the block’s functional descriptions. Each block is coded individually and may be simulated in a block-specific test bench. The team assembles the blocks into a device-level file where the ports are pins on the target device. The design is then ready to be compiled for simulation initiating the debug phase of development: Simulation followed by hardware debug.

Most simulation is performed using a testbench that is written by the designer. The testbench typically has clocks, reset, and control pins that operate on the design, and the signal assertion timing is specified in the testbench.