As field-programmable gate arrays (FPGAs) have grown in capacity, complexity and performance, their associated design and verification tools, infrastructures and methodologies have struggled to keep up. Today’s FPGAs may contain the equivalent of millions of logic gates and run hundreds of thousands of lines of embedded software. Such designs may involve multiple hardware design teams, software development teams and verification teams located around the globe. In order to address designs of this size and complexity it is necessary to employ what is known as hierarchical team-based design.

This paper first considers the evolution of FPGAs and FPGA design. Next, the concepts of top-down and divide-and-conquer design flows are introduced. Also discussed are considerations and capabilities required to support true hierarchical team-based design along with content management and design reuse considerations.