Articles – Page 204

January 2, 2014

Everybody’s seen one of those hyper dogs. You know, the little yappy ones that greet you with an intense, boundless energy, spinning like a furry maelstrom and wagging their tails so hard you wonder how they stay attached? And you’ve doubtless heard someone say something like, “Wow, if only we could harness that energy, we’d solve the world’s problems.” Heck, harnessing even the tail would be a monumental start.

Of course, we’re nowhere near doing that. But if we could coat that dog’s tail with a piezoelectric material, we could create … Read More → "Wag the Cantilever"

The Year in EDA

Did Anything Happen?

by Bryon Moyer

December 23, 2013

2013 is coming to a close, and this is usually a time for reflecting on what’s happened in the past year and what’s going to happen in the coming year. The thing is, though, when I sit back and reflect, well, I don’t know; it just seems like 2013 was a quiet year for EDA.

So I took a couple of approaches to reviewing the year. One is to see what the Big Guys did and the other was to solicit some other opinions as to what’s in and what’s out.

Why … Read More → "The Year in EDA"

Europe Takes on the World

by Dick Selwood

December 19, 2013

Two (relatively) recent announcements from Brussels have made it clear that the European Union is serious about pushing back into the electronics business. One, which initially looks like a bureaucratic reshuffle with added jargon, is that three programs, ARTEMIS, ENIAC and EPoSS are being merged into a Joint Undertaking / Public Private Partnership to be called ECSEL. I will translate this in a moment. The other announcement was an aspirational target – that Europe should double chip manufacture to reach 20% of the world output, and more than domestic US output, by 2020.

Both these initiatives are being driven by the … Read More → "Europe Takes on the World"

Rockin’ It Industrial Style

Fans of Heavy Metal Will Like TI’s New Delfino MCU

by Jim Turley

December 18, 2013

Are you into heavy metal? Do power generation, motor control, PLCs, robotics, and automation rock your socks off? Does spinning metallica make you want to raise your fist and yell? Then grab your lighters, motörheads. Stuff’s about to get real.

The number of this beast is F2837xD (it probably means something if you say it backwards), and it comes out of Texas. Dallas, to be exact, and more specifically, TI. Within the walls of TI’s black metal warehouse it’s called Delfino because, well, F2837xD is too hard to pronounce when you’ … Read More → "Rockin’ It Industrial Style"

Imaging Without Lenses

Apparently That Makes Sense

by Bryon Moyer

December 16, 2013

A simple-sounding-yet-bizarre notion has been frequenting certain optical research spots. It’s the concept of a “lens-free” imaging system. I’ve found no mentions that bother to explain exactly what that means.

Perhaps that’s because it should be obvious: you need no lens. Duh…

You know, it’s been a long time since I studied optics in college physics. And once my career was plotted on the digital scale, my mathematical tendencies have been spoiled by a solution space that gives you a 50:50 chance of being right just by guessing. Things are either 1 or 0. ( … Read More → "Imaging Without Lenses"

Sensor Hub Partitioning

Not Just Software vs. Hardware

by Bryon Moyer

December 12, 2013

We recently took a look at Lattice’s approach to sensor hubs. We’ve seen many other ways of implementing sensor hubs in the past, but all of those were software-based; it was just a question of where the software executes. Lattice’s approach is hardware, and that raises all kinds of new questions.

The biggest red flag that it raises for me is that moving a task from … Read More → "Sensor Hub Partitioning"

Andes Processor Keeps a Low Profile

Taiwanese CPU Company is Happy to Keep Cool, Cash Checks

by Jim Turley

December 11, 2013

You know that feeling when you discover a great little restaurant that nobody else knows about? Or listen to a terrific band that’s flying under the radar?

That’s how the designers of a few hundred million SoCs must feel. They’ve discovered the Andes, a small 32-bit microprocessor core that sits in the middle of a burgeoning array of small-scale electronic devices. Once known only to the Asian cognoscenti, Andes is going global, including a push into the United States. Who knows – Andes may even be seen in South America before long.

A Bonus Generation

Xilinx Rolls UltraScale

by Kevin Morris

December 10, 2013

The FPGA world has a unique obsession with semiconductor process nodes. Every two years or so we witness an epic battle between the two major market-share holders, centered mostly around who gets their devices working first on the next new semiconductor process. Historically, the stakes were very high. With FPGAs being among the first devices to go to production on a new node, and with the high-margin spoils of victory going largely to the winner – the biennial financial fates of the two big FPGA companies rode heavily on winning the next-generation derby.

Now, … Read More → "A Bonus Generation"

Flexible, Transparent Silicon?

A New Approach from KAUST

by Bryon Moyer

December 9, 2013

When you think of silicon, what characteristics come to mind? Soft and pliable? Or hard and edgy? Well, your basic silicon chip isn’t something you’d want floating free in your arteries as part of some health monitor; you’d want something covering it to smooth the edges.

Even the semi-liquid form of silicon’s oxide – glass – isn’t exactly associated with soft and gentle. Given that silicon chips are largely made of layers of silicon and silicon dioxide, well, it’ … Read More → "Flexible, Transparent Silicon?"

X-Verification Methodology for Both Designers and Verification Engineers

by Bryon Moyer

December 5, 2013

The propagation of unknown (X) states has become a more urgent issue with the move toward billion-gate SoC designs. The sheer complexity and the common use of complex power management schemes increase the likelihood of an unknown ‘X’ state in the design translating into a functional bug in the final silicon. This article describes a methodology that enables design and verification engineers to focus on the X states that represent a real risk, and to set aside those that are artifacts of the design process. The goal is to reduce project time, particularly time spent in simulation, and overcome … Read More → "X-Verification Methodology for Both Designers and Verification Engineers"