feature article
Subscribe Now

Europe Takes on the World

Two (relatively) recent announcements from Brussels have made it clear that the European Union is serious about pushing back into the electronics business. One, which initially looks like a bureaucratic reshuffle with added jargon, is that three programs, ARTEMIS, ENIAC and EPoSS are being merged into a Joint Undertaking / Public Private Partnership to be called ECSEL. I will translate this in a moment. The other announcement was an aspirational target – that Europe should double chip manufacture to reach 20% of the world output, and more than domestic US output, by 2020.

Both these initiatives are being driven by the Euro Commissioner for the Digital Agenda, Neelie Kroes, who has said, “I’m not a politician…  I’m Dutch – I tell it bluntly.”

First let’s have some context. The European Union is the over-arching organisation of 28 European Countries, with the aim of, amongst other things, creating a strong European economy. To achieve this aim in the 21st century, there has to be a digital dimension. Commissioner Kroes has said, “I want to see a vibrant European digital economy.”

Because of all the different countries and languages in the EU, everything is spelt out in excruciating detail in an attempt to avoid confusion and misunderstanding, but the resulting documents are often written in a strange version of English, with a whole new vocabulary. How this translates into the other languages is a subject of wonder.  One of the new buzzwords is KETs, Key Enabling Technologies. KETs are the areas where developing a strong European competence will, it is hoped, be the driver for a competitive economy. The KETs are nanotechnology, micro and nano-electronics, photonics, advanced materials, industrial biotechnology, and advanced manufacturing systems. Our interest, and that of Commissioner Kroes, is nanoelectronics, though other KETs feed into this. The EU seems to have dropped microelectronics as a term; all their discussions are about nanoelectronics.

(As a side note – it is typical, I fear, of the focus of many within the EU bureaucracy, that a document discussing progress on developing the KETs managed, in the course of over 7500 words – roughly five times the length of this article – not to list what the KETs are.)

The Digital Agenda covers things like digital infrastructure – Commissioner Kroes is pushing for faster digital networks, both wired and wireless, and she has begun to reign in the cell phone service providers, forcing them to reduce international roaming charges. But with nanoelectronics she has become passionate. In a recent speech she said, “I want to see a vibrant European digital economy,” which, she went on to emphasise, requires a strong nanoelectronics industry.

For chip manufacturing, she uses the analogy of Airbus, which started life as a consortium of struggling European companies and is now competing on level terms with Boeing. With financial support from the EU, and from national and regional governments, electronics companies will be encouraged to cooperate and invest in new manufacturing capabilities. This has been called the 10/100/20 strategy- that is, Euro 10 billion from EU co-funded projects and a Euro 100 billion investment from industry should produce 20% of the global manufacturing. (Currency note: the Euro is, as I write, US $1.37 – so 10 billion Euros is $13.7 billion)

There will be three complementary threads

  • Making Chips Cheaper (by transition to 450mm silicon wafers)
  • Making Chips Faster (More Moore technologies)
  • Making Chips Smarter (More than Moore technologies)

The strategy will be to try to exploit the significant electronics clusters – Grenoble, Dresden (Silicon Saxony), and Leuven/Eindhoven.

There are some obvious issues. With the exception of a few Integrated Device Manufacturers, chip manufacturing worldwide is mainly in the hands of foundries, massively dominated by TSMC. Europe has a number of small, usually specialist, foundries, but the only big-league player to have a presence is GlobalFoundries in Dresden. So who is going to be building and running these new fabs?

One indication might be gained from those companies active in the EEM450PR programme. This is a consortium running under the ENIAC programme to build a 450 mm pilot line at IMEC in Belgium. Intel, which has significant manufacturing in Ireland, is involved both with this and with the complementary Enable 450 programme. But the three European IEDMs – Infineon, ST and NXP – are not. However they don’t appear to have closed the door on getting involved, as the CEOs of all three companies are taking part in the European Leaders Group, a panel of industry leaders that is due to present a plan on how the targets can be achieved.

In parallel with this is the decision to merge ARTEMIS, ENIAC and EPoSS into a new programme called ECSEL.

Into the alphabet soup, then. Each of these acronyms is a Joint Undertaking, sometimes called a Joint Technology Initiative and sometimes a Public Private Partnership. They are programmes of multiple co-operative research projects, each involving government, industry, and academic partners from across Europe. There is normally an industry association, which compiles a Strategic Research Agenda, and then the Joint Undertaking reviews proposals for research within the framework of the strategic agenda, provides some funding, and monitors the work and provides strategic guidance. The argument is that big problems in technology can be solved only by pulling together resources from a range of companies. Finance comes from the European Union and from national governments and regional governments, and industry contributes resources of people and facilities.

I wrote about ARTEMIS a year ago but, in summary, ARTEMIS (Advanced Research and Technology for Embedded Intelligence and System) is focused on embedded systems, an area the EU identified as important some years ago. The abstract body is advised by council representing the people actually carrying out the work. This is called ARTEMISIA (ARTEMIS Industry Association) So far ARTEMIS has sponsored around 50 projects, and most of them have been completed. As I noted in the article last year, the results are often available only to the participants, except for high-level overviews, and the projects were strictly pre-commercialisation. However there has been a move towards what the programme is calling innovation – which seems to mean taking the results and using them in real commercial activities. Towards this end they are funding ARTEMIS Innovation Pilot Projects (AIPPs), and the first of these is CRYSTAL (CRitical sYSTem engineering AcceLeration). This, like the other AIPPs, will build on previous projects with the aim of “translating the knowledge into applications”. In this case CRYSTAL will aim “to establish and push forward an Interoperability Specification (IOS) and a Reference Technology Platform (RTP) as a European standard for safety-critical systems”. This will be an enormous project with 71 partners, including universities, research centres, and commercial companies ranging from giants to small and medium enterprises (SMEs) from Aerospace, Automotive, Healthcare and Rail, and with 10 different countries, and with a budget of more than 82 million Euros. (But bear in mind some of this budget is measured by the way that commercial organisations and the academic teams place a value on employee time.) Alongside ARTEMIS is ENIAC (European Nanoelectronics Initiative Advisory Council). This concentrates on nanoelectronics with a focus on five Applications

  1. Automotive and Transport
  2. Communications and Digital Lifestyle
  3. Energy Efficiency
  4. Health and Aging Society
  5. Safety and Security

And three Technologies

  1. Design Technologies
  2. Semiconductor Process and Integration
  3. Equipment, Materials and Manufacturing

Again, there is an associated industry body, Aeneas (Association for European NanoElectronics ActivitieS. Some of the current projects include the 450mm pilot line, mentioned above, Gallium Nitride Substrates, production of power semis, MEMS, FDSoI (Fully Depleted Silicon on Insulator – an alternative approach to FinFET). Application specific projects include power conversion, active implants for alleviating neurological problems, and power devices for automotive applications.

The third member of the new body is EPoSS – The European Technology Platform on Smart Systems Integration. Smart Systems are “…defined as intelligent, often miniatur­ised, technical subsystems with their own and independent functionality evolving from microsystems technol­ogy…” They normally involve sensors and actuators and may have communications capability.

Now it is easy to see that there are areas in common between these three programmes, and, as part of the tighter focus that Commissioner Kroes is pushing, it has been decided that they should be merged. This turns out to be more complicated than it sounds, as the industry bodies are legal entities, and pulling them together requires enormous amounts of lawyers’ work. (And, it is to be supposed, expense.) Subject to the work being completed on schedule, the intention is that ECSEL (Electronic Components and Systems for European Leadership), a new JTI (Joint Technology Initiative), is due to go live in early 2014. 

One of the important areas the ECSEL will be exploring is expressed in a piece of jargon that has been around in academic and government circles for some time, but is only now breaking out into the wild –  cyber-physical systems (CPS). The definitions are almost as varied as people using the phrase want them to be, but it seems in essence that a CPS has multiple interfaces to the world through multiple sensors and activators, and these communicate with each other and some areas of intelligence. For example, a car might, in some lights, be seen as a mobile CPS. The Internet of Things is another way of expressing the same idea. The focus of the different elements going into ECSEL can be seen to be combining to address the development of CPS, using the silicon created by the new fabs that will be produced under the manufacturing system.

This is a lovely programme, and, in an ideal world, it would be a winner. But we don’t live in an ideal world, and so the jury is out. The next milestones are the report of the European Leaders Group on how the manufacturing targets can be achieved, and, in a few months’ time, the launch of ECSEL. I will keep you posted.

One thought on “Europe Takes on the World”

Leave a Reply

featured blogs
Sep 21, 2023
Wireless communication in workplace wearables protects and boosts the occupational safety and productivity of industrial workers and front-line teams....
Sep 21, 2023
Labforge is a Waterloo, Ontario-based company that designs, builds, and manufactures smart cameras used in industrial automation and defense applications. By bringing artificial intelligence (AI) into their vision systems with Cadence , they can automate tasks that are diffic...
Sep 21, 2023
At Qualcomm AI Research, we are working on applications of generative modelling to embodied AI and robotics, in order to enable more capabilities in robotics....
Sep 21, 2023
Not knowing all the stuff I don't know didn't come easy. I've had to read a lot of books to get where I am....
Sep 21, 2023
See how we're accelerating the multi-die system chip design flow with partner Samsung Foundry, making it easier to meet PPA and time-to-market goals.The post Samsung Foundry and Synopsys Accelerate Multi-Die System Design appeared first on Chip Design....

Featured Video

Chiplet Architecture Accelerates Delivery of Industry-Leading Intel® FPGA Features and Capabilities

Sponsored by Intel

With each generation, packing millions of transistors onto shrinking dies gets more challenging. But we are continuing to change the game with advanced, targeted FPGAs for your needs. In this video, you’ll discover how Intel®’s chiplet-based approach to FPGAs delivers the latest capabilities faster than ever. Find out how we deliver on the promise of Moore’s law and push the boundaries with future innovations such as pathfinding options for chip-to-chip optical communication, exploring new ways to deliver better AI, and adopting UCIe standards in our next-generation FPGAs.

To learn more about chiplet architecture in Intel FPGA devices visit https://intel.ly/45B65Ij

featured paper

Accelerating Monte Carlo Simulations for Faster Statistical Variation Analysis, Debugging, and Signoff of Circuit Functionality

Sponsored by Cadence Design Systems

Predicting the probability of failed ICs has become difficult with aggressive process scaling and large-volume manufacturing. Learn how key EDA simulator technologies and methodologies enable fast (minimum number of simulations) and accurate high-sigma analysis.

Click to read more

featured chalk talk

Achieving High Power Density with IGBT and SiC Power Modules
Sponsored by Mouser Electronics and Infineon
Recent trends in the inverter market have made high power density, scalability, and ease of assembly more important than ever before. In this episode of Chalk Talk, Amelia Dalton and Abraham Markose from Infineon examine how Easy & Econo power modules from Infineon can help solve common inverter design requirements. They explore the benefits and construction of these modules and how you can take advantage of them in your next design.
May 19, 2023