When you think of silicon, what characteristics come to mind? Soft and pliable? Or hard and edgy? Well, your basic silicon chip isn’t something you’d want floating free in your arteries as part of some health monitor; you’d want something covering it to smooth the edges.
Even the semi-liquid form of silicon’s oxide – glass – isn’t exactly associated with soft and gentle. Given that silicon chips are largely made of layers of silicon and silicon dioxide, well, it’s why we call them “chips” instead of “drops” or “pads” or something else suitably soft.
Of course, having something flexible has obvious benefits. In order to do that, we typically turn to plastics. Those can be indisputably flexible. The challenge there, of course, is that organic circuitry doesn’t perform nearly as well as silicon does. Heck – just getting a complementary pair of transistors has proven challenging.
One of the main motivators of the flexibility of plastic is the prospect of printing circuits using roll-to-roll techniques, building electronics the way our forefathers printed newspapers. (Remember newspapers?) That can make for some pretty inexpensive circuitry. But if you need performance with your cheapness, well, organics still can’t cut it – by a wide margin.
So you’re back to solid, rough, sharp, mineral-based circuits. Yes, there are many options for such circuits, but if cheap is what you want, by silicon standards, so-called silicon (100) is the way to go. No, this isn’t a listing of the top 100 silicon manufacturers; this is the crystal orientation most commonly used for commercial purposes. That means that monstrous numbers of monstrous 300-mm wafers (and, perhaps someday, uber-monstrous 450-mm wafers) are made, accruing economies of scale – that is, making them cheap. Relatively.
The other thing that silicon isn’t is transparent. Plastics can be transparent (although the materials impregnated in them to make circuits might not be); silicon dioxide can be transparent; silicon? Not so much.
Then again, we’ve seen other applications where opaque materials like copper are used in a manner that appears transparent (or nearly so). So the concept of “transparency” can be a bit fuzzy.
Still and all, it’s in no way obvious that silicon might be made to be both transparent and flexible. And yes, that’s “silicon,” not “silicone.” But that is exactly what a team at KAUST (King Abdullah University of Science and Technology) has reported.
Their process requires some layout accommodations and a few more processing steps (including DRIE), but they say that the impact on cost shouldn’t be significant given the overall number of steps in a standard CMOS process. And, as we’ll see, there’s a re-use component that gets you some of your money back.
The idea is to arrange the layout so that inactive silicon areas (i.e., no diffusions) are placed 20 µm apart and at least 5 µm wide, effectively creating circuit islands that are 20×20 µm2 in a grid separated by 5- µm lanes. They then use DRIE to drill holes 20 µm apart deep into the silicon in those lanes. My rough math says that these holes are about 35 µm deep.
At this point, they put a thin layer of SiO2 over everything – and the critical point here appears to be that the inside walls of these holes get covered. That’s important for protecting the holes during an upcoming isotropic etch.
You can imagine that such an etch might be a problem if the top silicon surface were bare; similarly, the holes, if unprotected, would blow out in the presence of an isotropic etchant. After all, any exposed silicon in any direction would be eaten away. So this thin oxide film covers all; the hole bottoms are then cleared with an anisotropic etch, leaving the hole walls protected. I have to assume there’s a masking step here as well to keep the surface of the wafer protected.
Now the only silicon exposed to the isotropic etch is at the bottom of the holes. And etch they do, creating caves or cavities with a 10-µm radius. This radius is no accident: because of the 20-µm sizing of the circuit islands, the caves will meet underneath the islands, releasing the entire upper layer of silicon. Think of the limestone under Florida or the Yucatan. Like that, but more controlled. They ensure a 25-µm separation between the tops of the caves and the device layer (which, given the 10-µm etch, is how I came up with the 35-µm hole-depth number).
This spalling off has a qualitative resemblance to the finer-grained SmartCut process that Soitec uses to slice thin layers for SOI wafers. Obviously, in this case, the surfaces at the bottom of the circuit silicon and the top of the now-separated bulk wafer have a rough, scallopey look to them; this is something they claim to have addressed on the circuit slice, but they haven’t published those results yet.
But a main characteristic that this shares with SmartCut is that the bottom portion can be reused. They planarize away the scalloping and then use what’s left for another circuit. They can get several layers from a standard wafer, which helps to offset some of the extra processing cost. (So far I haven’t seen any real cost calculations, which will, of course, depend on lots of other variables.) They do say that they sacrifice only 16% of the silicon area to make this work – which they say is comparable to what’s lost due to standard isolation techniques.
The new, thinner, perforated layer containing the circuits is now flexible. And, while the silicon itself remains opaque, apparently there are enough of these holes that you can now see through the chip like looking through a screen door. This might seem surprising, since you would think that there’s far more circuitry than holes.
But some quick calculations suggest that for each 20 µm of circuitry, there’s a 5-µm hole. If holes are at the corners of the island, and if you allocate ¼ of each hole to one island, then you effectively have one 5-µm hole’s worth of area (roughly 20 µm2) for each 400 µm2 of circuit. That’s around 5% hole, not a lot. Then again, looking at the pictures, you can see through it, but it would never be mistaken for glass. Semi-transparent might be a better word.
Their next big project is to create a flexible, [semi-]transparent microprocessor. In particular, they’re deriving some of their inspiration from the folding found in the brain.
I did accrue a few questions in writing this, and KAUST’s Prof. Muhammad Mustafa Hussein was kind enough to interrupt his travel to send me some answers just in time for publication. These are:
- Q: They mentioned that the area impact of this is comparable to that used by standard trench isolation. The way this was articulated made me wonder if they’re suggesting that this can replace isolation.
A: Turns out that these holes are smaller than the normal shallow trench isolation, and, in fact, with clever layout, they can be combined: the holes can be placed in the trenches for no (or little) net penalty.
- Q: What allows the material to flex? Is it due to the holes, or is it a matter of crystal stresses?
A: Any inorganic material, if thin enough, will flex. One of those things where our macro world changes at the nano level. The thinner the material, the more it can flex.
- Q: If it’s crystal stresses, how does that impact engineered strain and transistor performance?
A: This depends on which way you fold it. If the circuits are inside the fold, then surface stresses are compressive, and PMOS devices will run faster. Folded the other way, the stress is tensile, and NMOS devices will be enhanced.
- Q: How far can this be folded? Pictures show nominal folding, but if follow-up work is to emulate the brain, that would indicate a high degree of tight folding.
A: This depends on the thickness. They’ve played with thicknesses from 1 to 125 µm. And they’ve achieved a bending radius down to 5 mm.