feature article
Subscribe Now

Andes Processor Keeps a Low Profile

Taiwanese CPU Company is Happy to Keep Cool, Cash Checks

You know that feeling when you discover a great little restaurant that nobody else knows about? Or listen to a terrific band that’s flying under the radar?

That’s how the designers of a few hundred million SoCs must feel. They’ve discovered the Andes, a small 32-bit microprocessor core that sits in the middle of a burgeoning array of small-scale electronic devices. Once known only to the Asian cognoscenti, Andes is going global, including a push into the United States. Who knows – Andes may even be seen in South America before long.

With 50+ licensees and 300+ million units to its name, Andes is no small player in the embedded-processor market. It’s just very low key. The Taiwan-based firm has over 100 employees, with its key CPU designers working out of Sunnyvale, in the heart of Silicon Valley. The vast majority of those licensees are fellow Asian companies, producing a wide range of consumer electronics, wireless headsets, storage controllers, and the myriad other bits of hardware that propel our industry.

Like most other CPU-licensing companies – ARM, MIPS, and ARC come to mind – Andes offers a range of CPU cores, from high end to low end, intended to suit a range of customer requirements. In Andes’s case, the high-end devices don’t compete in quite the same league as, say, ARM’s Cortex-A57 or Imagination’s MIPS64 – we’re not talking that high end. Instead, the top-range Andes N13 stretches to reach 1 GHz in 40nm silicon, so it’s roughly comparable to an ARM11 or a midrange 32-bit MIPS core.

It’s at the opposite end of the spectrum that Andes has been most successful: very low-end CPU cores. Andes’s bread and butter is the N7, a dead-simple 32-bit CPU core design that aims to be small and cheap. Just the thing for Bluetooth headsets and the like. Its simple two-stage pipeline is about as elementary and unpretentious as you can get, yet it still delivers good integer performance. On the CoreMark benchmark, Andes says the N7 can crank out 2.62 CoreMark/MHz (the EEMBC website says 2.29), which is slightly better than an ARM Cortex-A8 or a Freescale Kinetis K70-series part. On the other hand, the Andes core was puttering along at just 30 MHz, while the others were well into triple-digit clock speeds. But if low and slow is your thing, Andes has a small and efficient way to get there.

How does the Andes instruction set compare to its rivals’ ISAs? Who knows? Andes doesn’t publish a detailed programmers’ reference manual, and most SoC designers don’t care, anyway. Suffice to say it gets the job done; you just won’t find a lot of third-party application software written specifically for Andes.

Having said that, the company has done a good job of corralling middleware and RTOS choices for the N7 and its stablemates. In addition to a Linux kernel, you have commercial options like ThreadX, Nucleus, uC/OS, and FreeRTOS. Not a bad collection for a processor most Western engineers have never heard of.

There’s also the obligatory Eclipse-based IDE, which Andes calls AndeSight. With a complete instruction-set simulator (ISS) and RTOS awareness, it’s clear that Andes isn’t new to the game. Currently, Andes’s own C/C++ compiler is the only option.

Andes, like ARC, appeals to designers of deeply embedded systems-on-chip: products that don’t need a lot of third-party software or broad support from commercial tools. They need a silicon engine to make their gizmo go, and the internals of that engine are somebody else’s problem. Among Andes’s clientele, performance is not much of an issue, but small die size and low power consumption are. They’re not looking for the latest in trendy processor technology (is there such a thing?); they just want a tool to get the job done. And Andes is standing by with tools in hand. You know what they say: Once you go Black & Decker, you never go back.  

11 thoughts on “Andes Processor Keeps a Low Profile”

  1. Pingback: car crash usa
  2. Pingback: jeux de friv
  3. Pingback: insulation
  4. Pingback: well trained dog
  5. Pingback: DMPK Services

Leave a Reply

featured blogs
Nov 25, 2020
It constantly amazes me how there are always multiple ways of doing things. The problem is that sometimes it'€™s hard to decide which option is best....
Nov 25, 2020
[From the last episode: We looked at what it takes to generate data that can be used to train machine-learning .] We take a break from learning how IoT technology works for one of our occasional posts on how IoT technology is used. In this case, we look at trucking fleet mana...
Nov 25, 2020
It might seem simple, but database units and accuracy directly relate to the artwork generated, and it is possible to misunderstand the artwork format as it relates to the board setup. Thirty years... [[ Click on the title to access the full blog on the Cadence Community sit...
Nov 23, 2020
Readers of the Samtec blog know we are always talking about next-gen speed. Current channels rates are running at 56 Gbps PAM4. However, system designers are starting to look at 112 Gbps PAM4 data rates. Intuition would say that bleeding edge data rates like 112 Gbps PAM4 onl...

featured video

Improve SoC-Level Verification Efficiency by Up to 10X

Sponsored by Cadence Design Systems

Chip-level testbench creation, multi-IP and CPU traffic generation, performance bottleneck identification, and data and cache-coherency verification all lack automation. The effort required to complete these tasks is error prone and time consuming. Discover how the Cadence® System VIP tool suite works seamlessly with its simulation, emulation, and prototyping engines to automate chip-level verification and improve efficiency by ten times over existing manual processes.

Click here for more information about System VIP

Featured paper

Top 9 design questions about digital isolators

Sponsored by Texas Instruments

Looking for more information about digital isolators? We’re here to help. Based on TI E2E™ support forum feedback, we compiled a list of the most frequently asked questions about digital isolator design challenges. This article covers questions such as, “What is the logic state of a digital isolator with no input signal?”, and “Can you leave unused channel pins on a digital isolator floating?”

Click here to download the whitepaper

Featured Chalk Talk

Microchip PIC-IoT WG Development Board

Sponsored by Mouser Electronics and Microchip

In getting your IoT design to market, you need to consider scalability into manufacturing, ease of use, cloud connectivity, security, and a host of other critical issues. In this episode of Chalk Talk, Amelia Dalton sits down with Jule Ann Baker of Microchip to chat about these issues, and how the Microchip PIC-IoT WG development board can help you overcome them.

Click here for more information about Microchip Technology PIC-IoT WG Development Board (AC164164)