Future Proofing Your FinFET Design
Building a custom chip on the latest 16nm FinFET processes is a mind-bogglingly challenging, risky, and expensive proposition. Non-recurring engineering costs have skyrocketed in recent years, and the complexity of doing a design on the latest process nodes is sobering for even the most experienced design teams. Schedules have stretched, and fear of the dreaded respin has ramped up to abject terror as the stakes have continued to rise.
But what if you could hedge your bets? What if you could bring the power and flexibility of programmable logic fabric to the critical … Read More → "Future Proofing Your FinFET Design"

