feature article
Subscribe Now

WHITE PAPER – Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints

altera.jpg

Introduction

Altera first introduced the 180-nm CMOS-technology HardCopy® series of ASICs, with their “seamless prototyping” capabilities, in 2001. The premise behind this first-generation HardCopy ASIC product was to “harden” the look-up table (LUT) structure of the FPGA and replace the programmable switch fabric with a direct wire (ASIC) interconnect using a small number of customized interconnect layers. Other blocks of “hardened” logic in the FPGA prototype, including I/Os, phase-locked loops (PLLs), memories, and serializer/deserializer (SERDES) channels, are used verbatim in the HardCopy ASIC. Since the introduction of that first-generation device, Altera has offered subsequent HardCopy ASIC products in 130-nm, 90-nm, and 40-nm CMOS technology. The HardCopy ASIC has attributes similar to gate array technology in that common partially fabricated “bases” are staged in inventory. The tape-out of a specific design results in a two-metal/two-via set of masks of custom metallization layers that define aunique device. The base wafer is then processed with custom metal masks, and tested and assembled in a package that is 100 percent socket-compatible and based on the same silicon process as the FPGA prototype.

This new HardCopy ASIC results in lower NRE costs versus comparable standard-cell implementations, and reduces the time to fabricate the ASIC since base wafers are pre-staged up to the custom interconnect wafer processing steps. The HardCopy ASIC is feature-equivalent to the corresponding Altera® Stratix® series FPGA, and offers comparable resources as the FPGA but with reduced die size and power. The final HardCopy ASIC is a pin-for-pin replacement of the FPGA prototype; therefore, the same system board and software can be retained between prototyping/field  trials and the final production device. Additional overall board savings can be realized by using the HardCopy ASIC for production, since it requires no boot device. The flash memory boot device does not need to be mounted on the HardCopy version of the board.

Author: Larry Landis, Senior HardCopy Project Manager, HardCopy Product Group, Altera Corporation


Leave a Reply

featured blogs
Apr 2, 2026
Build, code, and explore with your own AI-powered Mars rover kit, inspired by NASA's Perseverance mission....

featured paper

Quickly and accurately identify inter-domain leakage issues in IC designs

Sponsored by Siemens Digital Industries Software

Power domain leakage is a major IC reliability issue, often missed by traditional tools. This white paper describes challenges of identifying leakage, types of false results, and presents Siemens EDA’s Insight Analyzer. The tool proactively finds true leakage paths, filters out false positives, and helps circuit designers quickly fix risks—enabling more robust, reliable chip designs. With detailed, context-aware analysis, designers save time and improve silicon quality.

Click to read more

featured chalk talk

Nexperia GaN Power Proliferating in All Things Motor Control/Drive
Sponsored by Mouser Electronics and Nexperia
In this episode of Chalk Talk, Art Gonsky from Nexperia and Amelia Dalton discuss the biggest challenges of electric motors and controllers and how GaN power solutions can help solve these issues. They  also investigate how silicon, silicon carbide and GaN power solutions compare and how Nexperia and NXP technologies can get your next motor control design up and running in no time!     
Mar 25, 2026
28,801 views