editor's blog
Subscribe Now

Sticking With their Story: Zeno Demonstrates 1T SRAM at Leading Nodes

Let’s face it: We’re addicted to SRAM. It’s big, it’s power-hungry, but it’s fast. And no matter how much we complain about it, we still use it. Because we don’t have anything better in the mainstream yet.

We’ve looked at attempts to improve conventional SRAM. We’ve looked at completely different memory technologies that might be in line to replace SRAM, like RRAM (first more than five years ago, then last year – and we’re still working on it) and MRAM. And, a couple of years ago, we looked at one attempt to create a new SRAM technology out of conventional transistors – to be clear, just one such transistor (instead of six), plus a possible select transistor.

The company was Zeno, and they were even leveraging this idea as a way to provide greater drive in a transistor – possibly meaning one could stick with older technologies for longer. But, back in the memory story, there was at least one unknown – granted, a “we think so,” but without proof.

Here’s the thing: the original technology was proven on 28-nm planar technology. Could it be leveraged onto more aggressive nodes – ones with FinFETs? While Zeno thought it should work, they hadn’t run the experiments yet to prove it.

And it turns out that there was another nagging question – one of the little details that can sabotage a great new idea. The technology was originally implemented with a buried N-well below the transistor. This wasn’t – and isn’t – part of a standard CMOS flow. Yeah, it’s possible to change flows over time, but it’s super hard, and there better be a dang good payoff from it. Is a 1T SRAM cell enough to motivate that? Perhaps, but the other question to ask – and the one that Zeno asked – is, “Is that modification to the flow really necessary? What happens if we omit the buried N well. Will it still work?”

At this year’s IEDM, they came back and reported on those two items – both in a discussion and in a paper that they presented. And the answer to the two questions is: Yes.

The next figure shows the layout at 14 nm, with a 6T conventional SRAM on the left and their 1T version on the right.

(Image courtesy IEDM/Zeno)

They also showed the “profile” at 14 nm as compared to the original 28-nm planar version. Note both the use of a FinFET and the absence of the underlying n-well on the right. This latest rendition uses the standard foundry CMOS process.

(Image courtesy IEDM/Zeno)

They presented data showing the stability of the bistable element as data is read repeatedly, showing it sticks around – and that the read operation isn’t destructive.

(Image courtesy IEDM/Zeno)

And they presented lots more detail on reading and writing results in their paper. If you have access to the IEDM proceedings, look for, “A Bi-stable 1- /2-Transistor SRAM in 14 nm FinFET Technology for High Density / High Performance Embedded Applications.

 

More info:

Zeno

One thought on “Sticking With their Story: Zeno Demonstrates 1T SRAM at Leading Nodes”

Leave a Reply

featured blogs
Jul 29, 2021
Circuit checks enable you to analyze typical design problems, such as high impedance nodes, leakage paths between power supplies, timing errors, power issues, connectivity problems, or extreme rise... [[ Click on the title to access the full blog on the Cadence Community sit...
Jul 29, 2021
Learn why SoC emulation is the next frontier for power system optimization, helping chip designers shift power verification left in the SoC design flow. The post Why Wait Days for Results? The Next Frontier for Power Verification appeared first on From Silicon To Software....
Jul 28, 2021
Here's a sticky problem. What if the entire Earth was instantaneously replaced with an equal volume of closely packed, but uncompressed blueberries?...
Jul 9, 2021
Do you have questions about using the Linux OS with FPGAs? Intel is holding another 'Ask an Expert' session and the topic is 'Using Linux with Intel® SoC FPGAs.' Come and ask our experts about the various Linux OS options available to use with the integrated Arm Cortex proc...

featured video

Accelerate Intelligent SLAM with DesignWare ARC EV Processor IP

Sponsored by Synopsys

Simultaneous localization and mapping (SLAM) algorithms build a map and determine location in the map at the same time. But how can you speed up the results? This demo shows how ARC EV processor IP with CNN engine accelerates KudanSLAM algorithms.

Click here for more information about DesignWare ARC EV Processors for Embedded Vision

featured paper

Carmakers charge ahead with electric vehicle powertrain integration

Sponsored by Texas Instruments

Advancements to electric vehicle (EV) powertrain architectures help customers cut system-design costs in half while maximizing power density, increasing efficiency, improving reliability, and making EVs more affordable for more people.

Click to read more

featured chalk talk

The Wireless Member of the DARWIN Family

Sponsored by Mouser Electronics and Maxim Integrated

MCUs continue to evolve based on increasing demands from designers. We expect our microcontrollers to do more than ever - better security, more performance, lower power consumption - and we want it all for less money, of course. In this episode of Chalk Talk, Amelia Dalton chats with Kris Ardis from Maxim Integrated about the new DARWIN line of low-power MCUs.

Click here for more information about Maxim Integrated MAX32665-MAX32668 UB Class Microcontroller