We saw the other day that Cadence was being aggressive with the memory controller IP from their Denali side. They’re actually trying to create a wider-scoped solution by providing a PCB package that ties in well with their DDR3 memory controller IP.
DDR memory timing is simply nuts, and board layout is critical. Everything matters. So the DDR3 Design-in kit contains the memory controller I/O and IC package model, timing/duration model, connector model, memory model, DIMM topology, and electrical constraints for the controller … Read More → "DDR3 System On-and-Around the Chip"