editor's blog
Subscribe Now

When Greater Extinction Is a Good Thing

Earlier this year we got some comment from French research consortium Leti on the photonics research they were doing and where they saw it going.

More recently, they’ve announced that their HELIOS project was able to achieve the first-ever 40 Gb/s optical modulator having  an extinction ratio (more or less like the noise margin, the power difference between a logic 0 and a logic 1 – why optical needs a different vocabulary, I don’t know…) of 10 db.

This was done on a CMOS-friendly process for straightforward integration with other circuits.

I asked what was done differently to achieve this, and they were somewhat coy, noting a “well-mastered design.” More specifically, “To insure a precise doping profile [, which] is mandatory for silicon depletion modulators, the patented self-alignment technique gave a well defined junction. Then optimization of the doping and fabrication of thick electrodes helped to achieve this [result] as well as optimized design for the RF electrodes.” They’re promising higher RF speeds in the future.

I also asked whether this was a proof-of-concept project, or whether the result was transferrable to commercial use. They said they used standard processing techniques, getting good yields on 200-mm wafers, so that, whenever the market is ready, this can be moved into production.

More info on their release

Leave a Reply

featured blogs
Jul 20, 2018
https://youtu.be/KwrfcMtbMDM Coming from CDNLive Japan (camera Asushi Tanaka) Monday: Nicolas's Recipe for Digital Marketing in EDA Tuesday: Embargoed announcement Wednesday: Trends, Technologies, and Regulation in China's Auto Market Thursday: Breakfast Bytes Guide...
Jul 19, 2018
In the footer of Samtec.com, we'€™ve always made it easy to contact us by phone, email, or live chat (even fax back in the day!). To continue to progress this theme, you'€™ll now find a new helpful tool in the footer area of Samtec.com. This tool will match you up with yo...
Jul 16, 2018
Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA'€™s configuration bits. Each Speedcore instance contains its own FPGA configu...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...