SLX FPGA v2019.4 Delivers an Average of 45X HLS Performance Improvement
San Jose, CA – December 16, 2019 – Silexica (silexica.com) has announced the release of SLX FPGA v19.4. Designed to help developers prepare and optimize C/C++ code for high-level synthesis (HLS) in Xilinx’s VivadoTM and VitisTM HLS design flows. SLX FPGA v19.4 provides performance improvements that deliver, on average, a 45x increase in performance by leveraging SLX’s FPGAs parallelism detection and automatic HLS pragma insertion when compared to no HLS pragmas.
Maximizing Design Performance
Adopting an HLS methodology presents challenges that … Read More → "SLX FPGA v2019.4 Delivers an Average of 45X HLS Performance Improvement"

