Aldec Enhances Riviera-PRO’s VHDL and UVVM Support
December 19, 2019
Henderson, USA – December 17, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added features to its Riviera-PRO functional verification platform that provide further support when working with the latest version of VHDL (2018) as well as the 2019.09.02 release of the Universal VHDL Verification Methodology (UVVM).
Users interested in benefiting from the latest developments in the VHDL standard, i.e. VHDL 1076-2018, can now use Riviera-PRO 2019.10 to access newer attributes and improvements of existing implementations of VHDL-2018, like the to_string function and ‘IMAGE attribute can … Read More → "Aldec Enhances Riviera-PRO’s VHDL and UVVM Support"
