industry news
Subscribe Now

Imec Develops 3D-Compatible Germanium nMOS Gate stack with High Mobility and Superior Reliability

SAN FRANCISCO – International Electron Devices Meeting 2016 (IEDM) – Dec. 7, 2016 – At this week’s IEEE IEDM conference, imec, the world-leading research and innovation hub in nano-electronics and digital technologies showed for the first time a silicon (Si)-passivated germanium (Ge) nMOS gate stack with dramatically reduced interface defect density (DIT) reaching the same level as a Si gate stack and with high mobility and reduced positive bias temperature instability (PBTI). These promising results pave the way to Ge-based finFETs and gate all-around devices, as promising options for 5nm and beyond logic devices.

Today’s results were achieved by band engineering using an interface dipole at high-k/SiO2 interface, and a H2 high-pressure anneal (HPA) finalizing the process flow. The interface dipole was formed on SiO2 layer by depositing a Lanthanum (La)SiO layer by atomic layer deposition (ALD), which is a 3D-compatible process. While a high DIT has been the leading concern for Si-passivated Ge nFET, it was dramatically reduced, for the first time, from 2×1012 cm-2eV-1 down to 5×1010 cm-2eV-1 around midgap using a combination of the LaSiO insertion and a H2 HPA. Consequently, electron mobility was increased (approximately 50 percent at peak) while PBTI reliability was improved thanks to the interface dipole-induced band engineering.

At IEEE IEDM, imec also presents a model for heterostructure interface resistivity (Rhi) analysis for highly doped semiconductors. Using this novel model, imec predicted that high-doping Si:P in a TiSix/Si:P/n-Ge contact stack helps to overcome the high contact resistance problem in Ge nMOS. With development of an advanced low-temperature Si:P epitaxy technique, imec demonstrated a TiSix/Si:P/n-Ge contact stack with record-low contact resistivity for n-Ge.

  “Dedicated to push the boundaries of Moore’s law, Ge-based devices are a key focus area or our research,” stated An Steegen, Executive Vice President Semiconductor Technology and Systems. “These breakthrough achievements underscore our dedication to understanding the fundamental roadblocks that need to be overcome in order for Ge-based devices to become a viable solution for 5nm and beyond.”

This work was performed in collaboration with ASM, Poongsan and Nanyang Technological University. Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony and TSMC.

This press release can be downloaded at http://www2.imec.be/be_en/press/imec-news/imec-IEDM-Ge-nMOS-devices.html

Energy band diagrams of Si-passivated Ge nFET (b) without interface dipole and (c) with interface dipole at the high-k/SiO2 interface.

DIT profile of Si-passivated Ge gate stacks improved by LaSiO insertion and HPA.

About imec

Imec is the world-leading research and innovation hub in nano-electronics and digital technologies. The combination of our widely acclaimed leadership in microchip technology and profound software and ICT expertise is what makes us unique. By leveraging our world-class infrastructure and local and global ecosystem of partners across a multitude of industries, we create groundbreaking innovation in application domains such as healthcare, smart cities and mobility, logistics and manufacturing, and energy.

As a trusted partner for companies, start-ups and universities we bring together close to 3,500 brilliant minds from over 70 nationalities. Imec is headquartered in Leuven, Belgium and also has distributed R&D groups at a number of Flemish universities, in the Netherlands, Taiwan, USA, China, and offices in India and Japan. In 2015, imec’s revenue (P&L) totaled 415 million euro and of iMinds which is integrated in imec as of September 21, 2016 52 million euro. Further information on imec can be found at www.imec.be.
Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a “stichting van openbaar nut”), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shanghai) Co. Ltd.) and imec India (Imec India Private Limited), imec Florida (IMEC USA nanoelectronics design center).

Leave a Reply

featured blogs
May 2, 2024
I'm envisioning what one of these pieces would look like on the wall of my office. It would look awesome!...
Apr 30, 2024
Analog IC design engineers need breakthrough technologies & chip design tools to solve modern challenges; learn more from our analog design panel at SNUG 2024.The post Why Analog Design Challenges Need Breakthrough Technologies appeared first on Chip Design....

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Intel AI Update
Sponsored by Mouser Electronics and Intel
In this episode of Chalk Talk, Amelia Dalton and Peter Tea from Intel explore how Intel is making AI implementation easier than ever before. They examine the typical workflows involved in artificial intelligence designs, the benefits that Intel’s scalable Xeon processor brings to AI projects, and how you can take advantage of the Intel AI ecosystem to further innovation in your next design.
Oct 6, 2023
26,481 views