SAN JOSE, CA – May 22, 2013 – ATopTech, the leader in next-generation physical design solutions that address the challenges of designing integrated circuits (ICs), today announced that Aprisa™ and Apogee™, the company’s place and route solution, have been certified by TSMC for 16nm FinFET v0.1 design enablement. TSMC’s leading 16nm FinFET technology offers improved design performance, lower overall power, and smaller area.
Aprisa and Apogee were certified in October 2012 by TSMC for 20nm design enablement with double patterning technology (DPT) routing rule support for TSMC’s 20nm reference flow. Aprisa’s innovative color-aware DPT routing technology uses a correct-by-construction approach that guarantees no missing DPT violations at signoff while achieving excellent routability and router runtime.
Aprisa and Apogee has subsequently gone through a rigorous 16nm FinFET certification process that includes signoff correlation checking of design rule checking (DRC), layout versus schematic (LVS), and formal verification to fulfill new process requirements such as new design rules for P-80 layers, 16nm FinFET transistor-related placement rules and DFM requirements.
“ATopTech’s technologies were purposed for just such advanced process technologies as TSMC 16nm FinFET,” said Jue-Hsien Chern, CEO of ATopTech. “This close collaboration with TSMC further enables our joint customers to take full advantage of the TSMC advanced technology for better product competitiveness.”
“ATopTech’s certification demonstrates significant ecosystem progress as we prepare our joint customers for 16nm FinFET design,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division.
About Aprisa
Aprisa is a complete place-and-route (P&R engine), including placement, clock tree synthesis, optimization, global routing and detailed routing. The core of the technology is its hierarchical database. Built upon the hierarchical database are common “analysis engines,” such as RC extraction, design rule checking (DRC) engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, signal integrity (SI) and multi-corner multi-mode (MCMM) analysis. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process. Because of this advanced architecture, Aprisa is able to deliver predictability and consistency throughout the flow, and hence faster total turn-around time (TAT) and best quality of results (QoR) for physical design projects.
About Apogee
Apogee is a full-featured, top-level physical implementation tool that includes prototyping, floor-planning, and chip-assembly. The unified hierarchical database enables a much more stream-lined hierarchical design flow. Unique In-Hierarchy-Optimization (iHO) technology helps to close top-level timing during Chip-Assembly through simultaneous optimization at top-level and at blocks, reducing the turn-around time for top-level timing closure from weeks to days.
About ATopTech
ATopTech, Inc. is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com
