industry news
Subscribe Now

Lattice Programmable Power Manager Device Reduces Cost Of Power Failure Protection For Solid State Drives

HILLSBORO, OR – June 11, 2012 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced power management solutions that will greatly simplify and increase the reliability of power failure protection circuitry in Solid State Drives (SSD).  The power failure protection circuitry prevents data loss in the event of input power failure by using the on-board hold-up capacitor to provide supplemental power during that critical period when the data is fully saved into the Flash memory.  These circuits traditionally use either a super capacitor or a tantalum capacitor bank along with a voltage boost converter to store the energy.

The innovative Lattice Power Manager II device simplifies and reduces the cost of power failure protection circuitry by integrating the charging and power switchover circuit of the hold-up capacitor. In the case of tantalum hold-up capacitor applications, it eliminates the need for a voltage boost converter.

“The power failure circuitry implemented using our Power Manager II devices can be used across a wide range of solid state drive architectures,” said Shakeel Peera, Senior Director of Strategic Marketing for Lattice Semiconductor. “These power management ICs can greatly lower system cost and free up board space by reducing the hold-up capacitor size.” 

Lattice’s Power Manager II devices enable the integration of super capacitor or tantalum capacitor charging and switchover, hot swap control, power fail interrupt and sequencing.  The Power Manager’s precision voltage monitoring (0.7% accuracy), fast response (48 microseconds) and on-chip CPLD greatly improve the reliability of the power failure protection circuitry in an SSD.  Faster system response, voltage doubler, capacitor voltage monitor and control circuitry reduce the amount of capacitance required to provide backup power during power outages.

Additional information about the use of Power Manager II devices in SSD design is available at www.latticesemi.com/SSDPOWER. 

Software Support for Power Manager II

Designs for the Power Manager II devices are implemented using the Lattice PAC-Designer® design software tools that are available for download free of charge at www.latticesemi.com/pac-designer. 

About the Power Manager II Family

The programmable Power Manager II family consists of six devices that can monitor and control up to 12 power supplies.  Within the family, the low power POWR607 device is ideal for portable SSD architectures, controlling up to six supplies and incorporating two high voltage MOSFET drivers.  The POWR1014 and POWR1220 devices are well suited for enterprise or PCIe SSD architectures.  The POWR1220 device can manage up to 12 voltages and drive 4 N-Channel MOSFETs for the most demanding SSD architectures.  It consists of a programmable threshold, precision differential input comparator block with an accuracy of 0.7%, a 48-macrocell CPLD, programmable hardware timers, a 10-bit analog to digital converter and a trim block for the trimming and margining of supplies.

All Lattice programmable mixed-signal product families are supported by development kits and reference designs that enable fast, easy product development. 

For more information about Power Manager II devices, visit http://www.latticesemi.com/products/powermanager.

About Lattice Semiconductor

Lattice is a service-driven developer of innovative low cost, low power programmable design solutions.  For more information about how our FPGA,CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via TwitterFacebook, or RSS.


Leave a Reply

featured blogs
May 8, 2024
Learn how artificial intelligence of things (AIoT) applications at the edge rely on TSMC's N12e manufacturing processes and specialized semiconductor IP.The post How Synopsys IP and TSMC’s N12e Process are Driving AIoT appeared first on Chip Design....
May 2, 2024
I'm envisioning what one of these pieces would look like on the wall of my office. It would look awesome!...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured paper

Altera® FPGAs and SoCs with FPGA AI Suite and OpenVINO™ Toolkit Drive Embedded/Edge AI/Machine Learning Applications

Sponsored by Intel

Describes the emerging use cases of FPGA-based AI inference in edge and custom AI applications, and software and hardware solutions for edge FPGA AI.

Click here to read more

featured chalk talk

Power High-Performance Applications with Renesas RA8 Series MCUs
Sponsored by Mouser Electronics and Renesas
In this episode of Chalk Talk, Amelia Dalton and Kavita Char from Renesas explore the first 32-bit MCUs based on the new Arm® Cortex® -M85 core. They investigate how these new MCUs bridge the gap between MCUs and MPUs, the advanced security features included in this new MCU portfolio, and how you can get started using the Renesas high performance RA8 series in your next design. 
Jan 9, 2024
17,718 views