When someone uses the words “verification” and “FPGA” in the same sentence, I’m always suspicious. In the ASIC design world, where risk avoidance is everything, “verification” is a sacred term. “Verification” is the long pole in the tent, the most time-consuming phase of the design cycle. “Verification” is what you do to protect your job so you’re not blamed with an expensive and time-consuming re-spin of an ASIC design. “Verification” is what EDA companies have learned to trust as their bread-and-butter. … Read More → "FPGA Simulation"