The 41st Design Automation Conference in San Diego last week wasn’t a bad conference. In fact, it was quite a good one. According to the program, there were a record number of papers submitted to the technical conference, and the selection panel had to be “more selective than ever” in choosing the elite few that were granted a session at DAC.
As a trade show, however, DAC is telegraphing ominous signals to the industry that supports it. Declining ASIC design starts, increasingly complex technical challenges, and rapidly improving alternative solutions threaten the very fabric of the EDA industry. The question is: is anyone listening? Do the three big EDA companies hear DAC’s whispered warnings that change is in the air? Do they realize that they might not be happy with where the new wind blows them?
There is an ironic gravity to the arrangement of booths on the trade show floor. The three traditional dominant suppliers of EDA tools, Synopsys, Cadence, and Mentor are anchored around the most distant periphery, one at each end and one in the center rear. Three established “spoilers” Magma, Aldec, and Synplicity are positioned at the front near the entrances. Large constellations of innovative startups circulate through the center of the exhibit space seeking stable orbits around potential suitors.
Interestingly, two of the largest suppliers of EDA tools (perhaps THE two largest suppliers depending on how you keep score) did not have booths at DAC. Altera and Xilinx probably provide more seats of design automation tools to more customers than any of the largest “EDA” companies. Certainly they each have more engineers dedicated to the development of FPGA tools than the three largest EDA companies combined. In fact, given the increasing tool sophistication required by new generations of FPGA technology, the cost of developing tools to support each successive generation may have surpassed the cost of developing the silicon architectures themselves. By this measure, Altera and Xilinx, the two largest FPGA companies, could in fact be EDA companies in disguise; exploiting a business model where revenue is derived from silicon sales rather than software seats.
It is said that those dealing with traumatic change experience a series of emotions beginning with anger, and then proceeding to denial, bargaining, depression, and acceptance. If companies are subject to these same emotions, it is possible that the large EDA suppliers are now somewhere between denial and bargaining.
The majority of the discussion, debate, and demonstration at the Design Automation Conference focused on the topic of cell-based ASIC design. The three largest companies in the industry held court in their traditional expansive booths with demonstrations galore of the latest ways to fend off the dreaded dragons of unintended NRE from ASIC re-spins, nasty nanometer effects, and complexity-induced confusion. Keynote addresses highlighted the fact that revenue on EDA tools comes in spurts, with each high-growth segment fueled by the creation of an innovative solution to a new, challenging problem (facing ASIC designers). Established tool markets quickly degenerate into low-growth commodity businesses. The question is: which new and challenging problems are being solved, and will the pursuit of those solutions ultimately lead to the success or failure of the companies that supply them?
Exhibitors at the Design Automation Conference outnumber attendees by a significant margin. It was even the source of slightly uncomfortable humor at the legendary and spectacular Denali customer party that the majority of the attendees were not, in fact, customers but competitors and other industry insiders. Real customers, both at the party and at the show, were a small but influential minority. According to industry statistics, the number of cell-based ASIC designs is in constant decline, with the cost and complexity of creating those designs on the rise. As the barriers to entry for ASIC design have continued grow, the number of companies with the resources and expertise to overcome those barriers has continued to decrease. The remaining few customers with the determination to continue require more and more sophisticated design tools, and are willing to pay more and more for the privilege of using them. This means large EDA companies chasing the ASIC dollar collect increasingly greater sums from a smaller and smaller pool of large customers.
These customers continue to fund the EDA industry, and continue to drive the creation of newer, more sophisticated products so that progress may continue to the next smaller geometry with its faster clock speeds, lower power consumption, and greater logic densities. If one plots these trends to their logical conclusion, EDA will eventually be trying to sell infinitely complex and expensive tools to an audience of none. It would seem, perhaps, that the EDA industry should begin to hedge its bets and provide products that address the broader, growing design market rather than this increasingly exclusive leading-edge.
When we talked with Geoffrey Moore in our “From Gordon to Geoffrey” article, he pointed out that there comes a time in any technology adoption cycle when the industry has to stop listening to its most trusted teacher customers; the “A” students who guided them to success, and instead start listening to the “B” and “C” students that make up the majority of the population. This is because the innovators will continue to lead technology companies down the trail of innovation-for-innovations’-sake, and at some point far surpass and diverge from the needs of the majority of the target market.
Why do the big EDA companies not invest in providing solutions for the multitudes of designers that comprise the mainstream market? The answer lies in the dynamics of the industry and the fact that the large EDA companies actually do very little innovation themselves. Most of the new products in EDA are developed by small startup companies. These small companies develop new, leading-edge, technologies to solve emerging problems. The successful ones are later acquired by big EDA companies.
A few, passionate, fortune seeking intellectuals with a modicum of startup funding can create a new EDA tool fairly easily. Five or six talented and dedicated software engineers in a garage can create products with an edge of creativity and a unity of vision that would be almost impossible to duplicate in a large corporate environment. What these startups do not have is sales channels. If you walk around the floor at DAC to all the 10X10 booths and ask how they plan to sell their new, cutting-edge, software-super-solution, you will generally hear that they plan to sell their product through “distribution.” On average, this answer is a lie. Almost no leading-edge EDA tools are sold by distributors. Distributors are good at selling semi-shrink-wrapped solutions to large low-touch audiences. Leading edge tools require massive support and hand-holding, and distributors simply are not equipped, qualified, or inclined to enter into such a business. The truth is that most of these EDA startups had their exit strategy planned by the time they were funded. Their mission is to make a few chosen customers successful through dedication and drive in order to attract the attention of a large EDA company with a checkbook and a channel to acquire them.
Usually, however, it is far easier, cheaper, and less risky for the large EDA companies to sit back and acquire the startups that clear the bar, than to burden themselves with myriad speculative design projects which may or may not come to business fruition. The cost of developing a new EDA tool is much smaller than the cost of bringing it to market, and the big EDA companies have the one thing that brings that cost under control: well-oiled sales channels that have strong, established relationships with the world’s 25 or so largest electronics companies.
While innovation in big EDA is rare, it is not unheard of. This year at DAC, for example, Mentor Graphics announced their “Catapult C” tool, a C/C++ to RTL synthesis technology that is worthy of notice for three reasons. First, it was developed internally at a major EDA company. Second, it solves a problem that is not specific to ASIC design, and is not directly related to “verification”. Third, being announced at DAC, it once again attempts to push DAC up the ladder of abstraction (see our “Cool and Groovy” article also this week).
There are other signs that big EDA is aware of the changing design market, and is trying to adapt. Cadence has started to more aggressively market its HDL simulation solutions to teams doing FPGA designs and, in fact, according to our 2003 FPGA market study, Cadence is the number two supplier of HDL simulation for FPGA (behind Mentor Graphics ModelSim). Cadence also has an OEM relationship with leading FPGA synthesis vendor Synplicity for reselling Synplicity’s tools as part of bundled solutions.
Synopsys too has made renewed efforts to respond to shifting market conditions, first with their announcement earlier this year of their return to the FPGA synthesis market with a new, prototyping-focused strategy, and more recently with their joint announcement with Altera to provide tools and services for Altera’s Stratix HardCopy program.
The problem is not that EDA doesn’t want to provide solutions to a broader market. They do. The problem is that big EDA is held hostage by their single greatest asset, their sales channel.
As EDA’s technology has adapted to the new reality of high-end design, its sales channels have adapted to the reality of the evolution of the ASIC customer. The majority of EDA revenue comes from a small number of very large companies in the form of term and remix deals where large pools of software licenses for vast arrays of products are provided based on multi-year contracts.
Unlike markets where customers are increasing in number, EDA sales channels do little prospecting for new leads. They already know most of the customers. What they do instead is “relationship management,” spending their energy maintaining close ties with the customers that constitute the gravy train, “protecting” them from any products deemed risky or potentially unstable (those are left for the startups to sell), and encouraging the largest possible renewal of the multi-year contract. They don’t want to risk the easy money from selling established, stable products by angering their customers with a piece of software that’s buggy or requires substantial hand-holding.
When EDA vendors go looking for new technology to acquire (or even develop), there is one key criterion. They choose products that they believe their channel can sell. The channel advises them based on the needs of their own trusted advisors, the decision makers at the elite few companies with the resources and expertise to do high-end ASIC design. If a startup’s new product solves a key problem for those companies, it is a prime target for big EDA acquisition. If it doesn’t fit the high-end ASIC mold, it likely will whither on the vine and die.
Even the competition between large vendors has settled into a state of complacent resignation. Each company has technology areas where they dominate the market, and each periodically launches a challenge at a part of the design flow neglected by the incumbent winner or works to capture a new emerging segment created by the rise of the latest unanticipated consequence of Moore’s Law. Real competition, however, is infrequent, as most companies consider the extreme cost and difficulty of displacing an entrenched market leader enough of a deterrent to remain content in their pre-carved niche. Like the arrangement of booths on the DAC floor, the big companies stay on their own side, careful not to infringe on the others’ turf, politely exchanging party invitations and slowly swapping employees.
What happens when the economics of chasing Moore’s law with cell-based ASICs no longer supports the industry required to do it? Already, the cost of moving up to a smaller process geometry is increasing exponentially while the usual three benefits of power, price, and performance have narrowed and required significant compromises to be made. When systems companies can no longer stomach the economics of cell-based design, they will simply move to alternative technologies such as structured ASIC and FPGA. With these more forgiving and more accessible technologies constantly making gains, they carve out increasingly large shares of the available electronics market that they can serve.
ASIC vendors are already adapting to those conditions by looking for new, more mass-marketable technologies such as structured ASIC to hedge their bets. They have a safe port when the storm comes. FPGA vendors have already positioned themselves to capture a growing segment of the low-and middle- tech segment of the application-specific semiconductor market, and are moving toward the FPGA/ASIC gap with increasing intensity. The ones left out in the cold are the big EDA companies. FPGA vendors have their own tool strategies well covered with no reliance on big EDA, and a few forward-thinking EDA companies like Synplicity and Aldec have built defensible positions in the expanding high-end FPGA and structured ASIC markets.
What does big EDA need to do to protect itself? The answer, unfortunately, is probably an overhaul of their sales, distribution, and support model. The inertia-to-impetus ratio for such a change is very high, however. It is easy for the well-paid EDA account manager, whose entire income relies on pleasing a specific large company, to listen to the growing challenges of his high-end customer as opportunities rather than threats. They reason that the more pain their customer experiences, the more opportunity they have to provide solutions to that pain at a premium price. What is not easy for that account manager to do is accept the inevitable reality that his customer will eventually be so overcome with pain that he will seek an altogether different approach to the problem and will no longer need the big EDA company to help him. Denial is a powerful emotion, and a very happy place.
If big EDA does not make such changes, however, and the majority of the electronics industry grows to rely on the newer “alternative” technologies for the development of new products, there will still be sophisticated design tools available. These tools will most likely be supplied by the FPGA vendors and by commercial EDA companies who have structured their sales channels to succeed with expanding rather than contracting customer bases. Their products will be accessible and supportable with minimal resources over large numbers of less-sophisticated customers, and they will be value-priced based on the productivity gains they offer rather than on the horrific product and schedule risk they help to avert.
Already there are signs that the change is starting. For example, Xilinx announced at DAC that they are acquiring EDA startup Hier Design. The acquisition makes good sense for Xilinx, as sophisticated incremental design will definitely be a key component of future high-end FPGA design. Cadence as well as Xilinx were investors in Hier Design during its startup phase. Such moves add fuel to an increasing trend of EDA startup acquisitions by companies other than the established three EDA vendors. As entrepreneurs see that there are other alternatives to the accepted EDA exit strategy, they will be emboldened to develop technologies that step outside the established ASIC-biased guidelines for success.
Change is in the EDA air, and if you listened you could hear the echoes of its quietly approaching footsteps at this year’s DAC. It will be interesting to see what happens.