feature article
Subscribe Now

Racing for the Gap

Altera and Synopsys go Structured

As suppliers jockey for position in offering products that hit the gap between the flexibility and risk-free design offered by FPGA and the performance and unit-cost advantages of cell-based ASIC, unlikely alliances are inevitable. In this case, ASIC design tool leader Synopsys is teaming with leading FPGA vendor Altera to jointly develop solutions for the design and production of Structured ASICs.

Altera has long touted their HardCopy structured ASIC as a clean cost-reduction path from an FPGA-based development, prototype, and early production platform to a cost-reduced, performance-optimized mask-programmed equivalent. Altera is betting that the advantages of programmable logic for early development will compel design teams to consider their structured ASIC offering.

The announcement this week says that Synopsys’s Galaxy design platform can now target Altera FPGA devices and their HardCopy structured ASIC counterparts, and that Synopsys Professional Services will support Altera’s HardCopy design centers. The partnership with Synopsys means that design teams already using Synopsys tools for ASIC design will have one less barrier to adopting an FPGA design methodology for future projects.

As Altera and other FPGA vendors diversify beyond their traditional applications and customer base, they are seeking ways to reduce unit cost, increase performance, and cut power consumption taking them closer to the capabilities of high-end ASIC while maintaining their substantial advantages in risk, schedule, flexibility, and design-cost. Altera’s strategy is somewhat unique among FPGA vendors as they are taking a mask-programmed approach similar to the ASIC suppliers rather than focusing on reducing the cost of a programmable logic fabric like rival Xilinx has with their Virtex-4 platform announced this week.

In going after the traditional ASIC market, Altera should gain leverage by partnering with Synopsys, whose synthesis and implementation tools are long time standards in the ASIC business. As ASIC designers look for alternatives to full cell-based implementation, the prospect of using their established design tools and methodologies, targeting an FPGA platform for development and prototyping, and cost-reducing with a low-risk, low-NRE path to a mask-programmed device should be quite attractive.

This also represents a move by Synopsys against synthesis rival Synplicity who has already staked a substantial claim and an early lead in the structured ASIC market. Synplicity already has a strong and visible track record in structured ASIC, partnering with silicon vendors and offering tools that leverage Synplicity’s FPGA experience and customer base. Structured ASIC represents one of the first markets where both companies are likely to compete on more equal footing as Synopsys has long been dominant in ASIC while Synplicity has dominated FPGA and neither has made a significant dent in the other’s dominance.

For both Synopsys and Altera, this agreement also represents a strategic alliance that helps them in diversifying into the others’ customer base in a complementary way. For a supplier of tools primarily to the cell-based ASIC market like Synopsys, it gives an opening to sell products to the larger, more diverse FPGA and structured ASIC market. For Altera, it represents cleaner access to the cell-based ASIC team by eliminating tool incompatibility as a barrier to adoption.

This assault on “the gap” is intensifying from all sides now, both in the silicon fabric space as well as the EDA space. More and more vendors are realizing that none of the current options squarely hits the sweet spot that many customers seek, and in the coming months we will see a variety of strategies to capture the lucrative eye of the custom logic hurricane.

Leave a Reply

featured blogs
Apr 24, 2019
In this week's Whiteboard Wednesdays video, Industry expert Rohit Kapur introduces the basic concepts of digital IC scan compression. Topics explained include the impacts of test application time... [[ Click on the title to access the full blog on the Cadence Community ...
Apr 23, 2019
Samtec Bulls Eye® test point systems are ideal for high-performance test applications because of their compression interfaces, small footprint, and high cycle count capabilities. Bulls Eye is now available in 50 GHz and 20 GHz designs, with a system up to 70 GHz in developme...
Apr 23, 2019
Move over, Information Age'€”the Autonomous Age is on its way. In the autonomous age, information is not just copious and accessible, it is integrated into our daily lives to automatically augment human capabilities. In the autonomous age, we expect technology to comprehend...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...