FPGA I/O Features Help Lower Overall PCB Costs
Introduction
High-end FPGAs with embedded processors, DSP and memory blocks are now replacing entire ASICs. New device families have accelerated programming times by dedicating several general-purpose I/O pins to create wider configuration buses that can then revert back to their primary I/O functionality. Rising device complexities imply high pin counts, which bring about new challenges and added costs when integrating these devices on the PCB. Design teams must now implement changes to ensure they do not negate the cost and time-to-market benefits of using programmable logic in the first place.
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